LTC4259CGW Linear Technology, LTC4259CGW Datasheet - Page 11

• Manufacturer Part Number: LTC4259CGW
• Manufacturer: Linear Technology

Specifications of LTC4259CGW

• Linear Misc Type: Negative Voltage
• Operating Supply Voltage (typ): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

REGISTER FU CTIO S
–26V). Bit 5 signals that the V
low the V
LTC4259 die temperature has exceeded its thermal shut-
down (TSD) limit. Thermal shutdown is intended to protect
against momentary overload conditions. Junction tempera-
ture will exceed 125 C while in thermal shutdown.
Continous operation above the specified maximum oper-
ating temperature may result in device degredation or fail-
ure. The logical OR of bits 1, 4, 5 and 7 appears in the
Interrupt register as the Supply Fault bit. See the Misc Config
register for information on masking the Osc Fail bit out of
the Supply Fault interrupt. The remaining bits in the regis-
ter are reserved and will always read as 0. The Supply Event
bits latch high and will remain high until cleared by reading
from address 0Bh.
Supply Event CoR (Address 0Bh): Supply Event Register,
Clear on Read. Read this address to clear the Fault Event
register. Address 0Bh returns the same data as address 0Ah,
and reading address 0Bh clears all bits at both addresses.
Status Registers
Port 1 Status (Address 0Ch): Port 1 Status Register, Read
Only. This register reports the most recent detection and
classification results for port 1. Bits 0-2 report the status
of the most recent detection attempt at the port and bits 4-6
report the status of the most recent classification attempt
at the port. If power is on, these bits report the detection/
classification status present just before power was turned
on. If power is turned off at the port for any reason, all bits
in this register will be cleared. See Table 1 for detection and
classification status bit encoding.
Port 2 Status (Address 0Dh): Port 2 Status Register, Read
Only. See Port 1 Status.
Port 3 Status (Address 0Eh): Port 3 Status Register, Read
Only. See Port 1 Status.
Port 4 Status (Address 0Fh): Port 4 Status Register, Read
Only. See Port 1 Status.
Power Status (Address 10h): Power Status Register, Read
Only. The lower four bits in this register report the switch
on/off state for the corresponding ports. The upper four
bits, the power good bits, indicate that the drop across the
power switch and sense resistor for the corresponding ports
is less than 2V, indicating that power start-up is complete
DD
UVLO threshold. Bit 7 indicates that the
U
DD
U
supply has dropped be-
and no current faults are present. The power good bits are
latched high and are only cleared when a port is turned off
or the LTC4259 is reset.
Pin Status (Address 11h): External Pin Status, Read Only.
This register reports the real time status of the external
AUTO (Pin 35), AUXIN (Pin 2), and AD0-AD3 (Pins 7-10).
The logic state of the AUTO pin appears at bit 0, the AUXIN
pin at bit 1, and the AD0-AD3 pins at bits 2-5. The remain-
ing bits are reserved and will read as 0. AUTO affects the
initial states of some of the LTC4259 configuration regis-
ters at start-up but has no effect after start-up and can be
used as a general purpose input if desired, as long as it is
guaranteed to be in the appropriate state at start-up.
Configuration Registers
Operating Mode (Address 12h): Operating Mode Configu-
ration, Read/Write. This register contains the mode bits for
each of the four ports in the LTC4259. See Table 1 for mode
bit encoding. At power-up, all bits in this register will be set
to the logic state of the AUTO pin (Pin 35). See Operating
Modes in the Applications Information section.
Disconnect Enable (Address 13h): Disconnect Enable
Register, Read/Write. The lower four bits of this register
enable or disable DC disconnect detection circuitry at the
corresponding port. If the DC Discon Enable bit is set the
port circuitry will turn off power if the current draw at the
port falls below I
R
IEEE 802.3af compliance. If the bit is clear the port will not
remove power due to low current.
The upper four bits enable or disable AC disconnect on the
corresponding port. When a port’s AC disconnect bit is set,
the LTC4259 senses the impedance of that port by forcing
an AC voltage on the port’s DETECT pin and measuring the
AC current. If the DETECT pin sinks less than I
more than t
the port will not remove power due to high port impedance
(AC current below I
The DC and AC disconnect signals are ORed together and
either sensing method (if they are both enabled) will keep
the port powered. A port with neither DC or AC disconnect
enabled will not power off automatically when the PD is
removed.
S
, where R
DIS
S
is the sense resistor and should be 0.5 for
, the port will turn off power. If the bit is clear,
MIN
for more than t
ACDMIN
).
DIS
. I
MIN
LTC4259
is equal to V
ACDMIN
11
MIN
4259i
for
/