LTC4259CGW Linear Technology, LTC4259CGW Datasheet - Page 18

• Manufacturer Part Number: LTC4259CGW
• Manufacturer: Linear Technology

Specifications of LTC4259CGW

• Linear Misc Type: Negative Voltage
• Operating Supply Voltage (typ): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4259
Foldback
Foldback is designed to limit power dissipation in the
MOSFET during short-circuit conditions and during power-
up. At low port output voltages, the voltage across the
MOSFET is high, and power dissipation will be large if
significant current is flowing. Foldback monitors the port
output voltage and reduces the V
linearly from its full value (212.5mV typ) at a port voltage
of 18V to approximately 1/7th of the full value (30mV typ)
at a port voltage of 0V. With 0.5 sense resistors, this
limits the short-circuit current to 60mA (typ) instead of the
full 425mA (typ) current limit. The V
old is also lowered to ensure that the current limit fault
timer runs while the port is in foldback current limit.
Short-Circuit Protection
If a port is suddenly shorted out, the MOSFET power
dissipation can rise to very high levels, jeopardizing the
MOSFET even before the normal current limit circuit can
respond. A separate short-circuit current limit circuit
watches for significant overcurrent events (V
>275mV, >550mA with a 0.5 sense resistor) and pulls
the GATE pin down immediately if such an event occurs,
shutting off the MOSFET in less than 1 s (with no external
capacitor on GATE). Approximately 100 s later, GATE is
allowed to rise back up and the normal current limit circuit
will take over, allowing I
t
reduced by the foldback feature to 1/7th of the nominal
value.
Choosing External MOSFETs
Power delivery to the ports is regulated with external
power MOSFETs. These MOSFETs are controlled as previ-
ously described to meet the IEEE 802.3af specification.
Under normal operation, once the port is powered and the
PD’s bypass capacitor is charged to the port voltage, the
external MOSFET dissipates very little power, at most FET
R
adequate for the job. Unfortunately, other requirements of
the IEEE 802.3af mandate a FET capable of dissipating
18
ICUT
ON
• (350mA)
timer to count up. During a short circuit, I
2
. This suggests that a small MOSFET is
U
LIM
U
current to flow and causing the
CUT
LIM
W
overcurrent thresh-
current limit level
U
LIM
will be
SENSE
significant power. When the port is being powered up, the
port voltage must reach 30V or more before the PD turns
on. The port voltage can then drop to 0V as the PD’s
bypass capacitor is charged. According to the IEEE, the PD
can directly connect a 180 F capacitor to the port and the
PSE must charge that capacitor with a current limit of
400mA to 450mA for at least 50ms.
An even more extreme example is a noncompliant PD that
provides the proper signature during detection but then
behaves like a low valued resistor, say 50 , in parallel with
a 1 F capacitor. When the PSE has charged this
noncompliant PD up to 20V, the 50 resistor will draw
400mA (the minimum IEEE prescribed I
keeping the port voltage at 20V for the remainder of t
The external MOSFET sees 24V to 37V V
450mA, dissipating 9.6W to 16.7W for 60ms (typ). The
LTC4259 implements foldback to reduce the current limit
when the MOSFET V
and the Typical Performance curves. Without foldback,
the MOSFET could see as much as 25.7W for 60ms (typ)
when powering a shorted or a noncompliant PD with only
a few ohms of resistance. Thanks to foldback, the MOSFET
sees a maximum 18W for the duration of t
The LTC4259’s duty cycle protection enforces 15 times
longer off time than on time, preventing successive at-
tempts to power a defective PD from damaging the
MOSFET. System software can enforce even longer wait
times. When the LTC4259 is operated in semiauto or
manual mode—described in more detail under Operating
Modes—it will not power on a port until commanded to do
so by the host controller. By keeping track of t
t
port again after one of these faults even if the LTC4259
reports a Detect Good. In this way the host controller
implements a MOSFET cooling off period which may be
programmed to protect smaller MOSFETs from repeated
thermal cycling. The LTC4259 has built-in duty cycle
protection for t
Timing sections) that is sufficient to protect the MOSFETs
shown in Figure 1.
ICUT
faults, the host controller can delay turning on the
ICUT
and t
DS
START
is high; see the Foldback section
(see t
ICUT
Timing and t
LIM
DS
START
current limit)
at 400mA to
START
.
START
START
and
4259i
.