LTC4259CGW Linear Technology, LTC4259CGW Datasheet - Page 23

• Manufacturer Part Number: LTC4259CGW
• Manufacturer: Linear Technology

Specifications of LTC4259CGW

• Linear Misc Type: Negative Voltage
• Operating Supply Voltage (typ): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
disconnect itself is a more thorough test of the OSCIN
signal. When the OSCIN signal is either absent or cor-
rupted, powered channels with AC disconnect enabled
(and DC disconnect not enabled) will automatically dis-
connect of their own accord in time t
is reset (by power on, Reset All bit or the RESET pin) the
Osc Fail bit is set. Once the Osc Fail bit is cleared, it will only
be set by an invalid signal on the OSCIN pin or another
reset.
SERIAL DIGITAL INTERFACE
The LTC4259 communicates with a host (master) using
the standard 2-wire interface as described in the SMBus
Specification Version 2.0 (available at http://smbus.org).
The SMBus is an extension of the I
LTC4259 is also compatible with the I
Timing Diagrams show the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL, must
be high when the bus is not in use. External pull-up
resistors or current sources, such as the LTC1694 SMBus
accelerator, are required on these lines. If the SDA and SCL
pull-ups are absent, not connected to the same positive
supply as the LTC4259’s V
when the power is applied to the LTC4259, it is possible for
the LTC4259 to see a START condition on the I
interrupt pin (INT) is only updated between I
tions. Therefore if the LTC4259 sees a START condition
when it powers up because the SCL and SDA lines were left
floating, it will not assert an interrupt (pull INT low) until
it sees a STOP condition on the bus. In a typical application
the I
will see a STOP so soon after power up that this momen-
tary condition will go unnoticed.
Isolating the Serial Digital Interface
IEEE 802.3af requires that network segments be electri-
cally isolated from the chassis ground of each network
interface device. However, the network segments are not
2
C bus will immediately have traffic and the LTC4259
U
U
DD
pin, or are not activated
W
DIS
2
C bus standard. The
. After the LTC4259
2
C bus, and the
2
2
C transac-
U
C bus. The
required to be isolated from each other provided that the
segments are connected to devices residing within a
single building on a single power distribution system.
For simple devices such as small powered Ethernet
switches, the requirement can be met by using an isolated
power supply to power the entire device. This implemen-
tation can only be used if the device has no electrically
conducting ports other than twisted-pair Ethernet. In this
case, the SDAIN and SDAOUT pins of the LTC4259 can be
connected together to act as a standard SDA pin.
If the device is part of a larger system, contains serial
ports, or must be referenced to protective ground for
some other reason, the Power over Ethernet subsystem
including the LTC4259s must be isolated from the rest of
the system. The LTC4259 includes separate pins (SDAIN
and SDAOUT) for the input and output functions of the
bidirectional data line. This eases the use of optocouplers
to isolate the data path between the LTC4259s and the
system controller. Figure 18 shows one possible imple-
mentation of an isolated interface. The SDAOUT pin of the
LTC4259 is designed to drive the inputs of an optocoupler
directly, but a standard I
used to buffer I
system controller side. Schmitt triggers must be used to
prevent extra edges on transitions of SDA and SCL.
Bus Addresses and Protocols
The LTC4259 is a read-write slave device. The master can
communicate with the LTC4259 using the Write Byte,
Read Byte and Receive Byte protocols. The LTC4259’s
primary serial bus address is (010A
nated by pins AD3-AD0. All LTC4259s also respond to the
address (0110000)b, allowing the host to write the same
command into all of the LTC4259s on a bus in a single
transaction. If the LTC4259 is asserting (pulling low) the
INT pin, it will also acknowledge the Alert Response
Address (0001100)b using the receive byte protocol.
2
C signals into the optocouplers from the
2
C device typically cannot. U1 is
3
A
2
A
LTC4259
1
A
0
)b, as desig-
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4259i