LTC4259CGW Linear Technology, LTC4259CGW Datasheet - Page 26

• Manufacturer Part Number: LTC4259CGW
• Manufacturer: Linear Technology

Specifications of LTC4259CGW

• Linear Misc Type: Negative Voltage
• Operating Supply Voltage (typ): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4259
asserting the INT pin, it acknowledges and sends its 7-bit
bus address (010A
While it is sending its address, it monitors the SDAIN pin
to see if another device is sending an address at the same
time using standard I
sending a 1 and reads a 0 on the SDAIN pin on the rising
edge of SCL, it assumes another device with a lower
address is sending and the LTC4259 immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC4259 will
stop pulling down the INT pin. When the INT pin is released
in this way or if a 1 is written into the Clear Interrupt pin bit
(bit 6 of register 1Ah), the condition causing the LTC4259
to pull the INT pin down must be removed before the
LTC4259 will be able to pull INT down again. This can be
done by reading and clearing the event registers or by
writing a 1 into the Clear All Interrupts bit (bit 7 of register
1Ah). The state of the INT pin can only change between I
transactions, so an interrupt is cleared or new interrupts
are generated after a transaction completes and before
new I
of the alert response address can be used instead of the
INT pin if desired. If any device acknowledges the alert
response address, then the INT line, if connected, would
have been low.
System Software Strategy
Control of the LTC4259 hinges on one decision, the
LTC4259’s operating mode. The three choices are de-
scribed under Operating Modes. In Auto mode the LTC4259
can operate autonomously without direction from a host
controller. Because LTC4259s running in Auto mode will
power every valid PD connected to them, the PSE must
have 15.4W/port available. To reduce the power require-
ments of the –48V supply, PSE systems can track power
usage, only turning on ports when sufficient power is
available. The IEEE describes this as a power allocation
algorithm and places two limitations: the PSE shall not
power a PD unless it can supply the maximum power for
that PD’s class and power allocation may not be based
26
2
C bus communication commences. Periodic polling
U
3
A
2
C bus arbitration. If the LTC4259 is
2
A
1
U
A
0
)b and a 1 (see Figure 10).
W
U
2
C
solely on a history of each PD’s power consumption. In
order for a PSE to implement power allocation, the PSE’s
processor/controller must control whether ports are pow-
ered—the LTC4259’s cannot operate in Auto mode.
Semiauto mode fits the bill as the LTC4259 automatically
detects and classifies PDs and makes this information
available to the host controller, which decides to apply
power or not. Operating the LTC4259 in Manual mode also
lets the controller decide whether to power the ports but
the controller must also control detection and classifica-
tion. If the host controller operates near the limit of its
computing resources, it may not be able to guide a Manual
mode LTC4259 through detect, class and port turn-on in
less than the IEEE maximum of 950ms.
In a typical PSE, the LTC4259s will operate in Semiauto
mode as this allows the host to decide to power a port
without burdening the controller. With an interrupt mask
of F4h, the LTC4259 will signal to the host after it has
successfully detected and classed a PD, at which point the
host can decide whether enough power is available and
command the LTC4259 to turn that port on. Similarly, the
LTC4259 will generate interrupts when a port’s power is
turned off. By reading the LTC4259’s interrupt register,
the host can determine if a port was turned off due to
overcurrent (t
removed (Disconnect event). The host then updates the
amount of available power to reflect the power no longer
consumed by the disconnected PD. Setting the MSB of
the interrupt mask causes the LTC4259 to communicate
fault conditions caused by failures within the PSE, so the
host does not need to poll to check that the LTC4259s are
operating properly. This interrupt driven system architec-
ture provides the controller with the final say on powering
ports at the same time, minimizing the controller’s com-
putation requirements because interrupts are only gener-
ated when a PD is discovered or on a fault condition.
The LTC4259 can also be used to power older powered
Ethernet devices that are not 802.3af compliant and may
be detected with other methods. Although the LTC4259
START
or t
ICUT
faults) or because the PD was
4259i