LTC4259CGW Linear Technology, LTC4259CGW Datasheet - Page 7

• Manufacturer Part Number: LTC4259CGW
• Manufacturer: Linear Technology

Specifications of LTC4259CGW

• Linear Misc Type: Negative Voltage
• Operating Supply Voltage (typ): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

PI FU CTIO S
RESET (Pin 1): Chip Reset, Active Low. When the RESET
pin is low, the LTC4259 is held inactive with all channels
off and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4259 begins normal
operation. RESET can be connected to an external capaci-
tor or RC network to provide a power turn-on delay. An
internal 50k resistor pulls RESET high if not externally
pulled down. Internal filtering of the RESET pin prevents
glitches less than 1 s from resetting the LTC4259.
AUXIN (Pin 2): Auxiliary Input. The real time state of the
AUXIN pin can be read at bit 1 in the Pin Status register
(11h). An internal 50k resistor pulls AUXIN low if it is left
floating. The AUXIN pin provides a simple way for the host
controller to read the state of a switch or other human
interface device.
INT (Pin 3): Interrupt Output, Open Drain. INT will pull low
when any one of several events occur in the LTC4259. It
will return to a high impedance state when bits 6 or 7 are
set in the Reset PB register (1Ah). The INT signal can be
used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See Register Functions and Applications
Information for more information. The INT pin is only
updated between I
SCL (Pin 4): Serial Clock Input. High impedance clock
input for the I
be connected directly to the I
SDAOUT (Pin 5): Serial Data Output, Open Drain Data
Output for the I
two pins to implement the bidirectional SDA function to
simplify optoisolation of the I
dard bidirectional SDA pin, tie SDAOUT and SDAIN to-
gether. See Applications Information for more information.
SDAIN (Pin 6): Serial Data Input. High impedance data input
for the I
to implement the bidirectional SDA function to simplify
optoisolation of the I
bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
U
2
C serial interface bus. The LTC4259 uses two pins
U
2
C serial interface bus. The SCL pin should
2
C Serial Interface Bus. The LTC4259 uses
2
C transactions.
U
2
C bus. To implement a standard
2
2
C bus. To implement a stan-
C SCL bus line.
AD3 (Pin 7): Address Bit 3. Tie the address pins high or low
to set the I
This address will be (010A
resistor pulls AD3 high if it is left floating.
AD2 (Pin 8): Address Bit 2. See AD3.
AD1 (Pin 9): Address Bit 1. See AD3.
AD0 (Pin 10): Address Bit 0. See AD3.
DETECT1 (Pin 11): Detection Sense, Channel 1. The
LTC4259 powered device (PD) detection and AC discon-
nect hardware monitors port 1 with this pin. Connect
DETECT1 to the port 1 output via a 100V 75mA signal
diode in parallel with a 0.2 F 100V X7R capacitor in series
with a 1k resistor (see Figure 1). The resistor and capacitor
may be eliminated if AC disconnect is not used.
DETECT2 (Pin 12): Detection Sense, Channel 2. See
DETECT1.
DETECT3 (Pin 13): Detection Sense, Channel 3. See
DETECT1.
DETECT4 (Pin 14): Detection Sense, Channel 4. See
DETECT1.
DGND (Pin 15): Digital Ground. DGND should be con-
nected to the return from the 3.3V supply. DGND and
AGND should typically be tied together. However, DGND
can be separated from AGND by as musch as 100mV and
remain IEEE compliant.
V
power supply relative to DGND. V
DGND near the LTC4259 with at least a 0.1 F capacitor.
SHDN1 (Pin 17): Shutdown Channel 1, Active Low. When
pulled low, SHDN1 shuts down channel 1, regardless of
the state of the internal registers. Pulling SHDN1 low is
equivalent to setting the Reset Port 1 bit in the Reset
Pushbutton register (1Ah). An internal 50k resistor pulls
SHDN1 high if it is left floating and an internal filter with a
time constant greater than 1 s prevents glitches from
shutting down the port.
DD
(Pin 16): Logic Power Supply. Connect to a 3.3V
2
C serial address to which LTC4259 responds.
3
A
2
A
DD
1
A
0
must be bypassed to
)
b.
LTC4259
An internal 50k
7
4259i