MT49H32M18CHT-25:A Micron Technology Inc, MT49H32M18CHT-25:A Datasheet - Page 12

• Manufacturer Part Number: MT49H32M18CHT-25:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18CHT-25:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 675mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 3:
PDF: 09005aef815b2df8/Source: 09005aef811ba111
576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN
WE#, REF#
QKx, QKx#
BA0–BA2
TMS, TDI
Symbol
DK, DK#
Q0–Q17
A0–A21
CK, CK#
D0–D17
QVLD
Vddq
TDO
Vext
Vssq
Vref
TCK
Vdd
CS#
DM
Vss
Vtt
ZQ
Ball Descriptions
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
Address inputs: A0–A21 define the row and column addresses for READ and WRITE
operations. During a MODE REGISTER SET, the address inputs define the register
settings. They are sampled at the rising edge of CK.
Bank address inputs: Select to the internal bank to which a command is being
applied.
Input clock: CK and CK# are differential input clocks. Addresses and commands are
latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH.
When the command decoder is disabled, new commands are ignored but internal
operations continue.
Data input: The D signals form the 18-bit input data bus. During WRITE commands,
the data is sampled at both edges of DK.
Input data clock: DK and DK# are the differential input data clocks. All input data is
referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. In
both x9 and x18 configurations, all Ds are referenced to DK and DK#.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is
masked when DM is sampled HIGH. DM is sampled on both edges of DK. Tie signal to
ground if not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is
not used.
IEEE 1149.1 clock input: This ball must be tied to Vss if the JTAG function is not used.
Input reference voltage: Nominally Vddq/2. Provides a reference voltage for the
input buffers.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define
(together with CS#) the command to be executed.
Data output: The Q signals form the 18-bit output data bus. During READ commands,
the data is referenced to both edges of QK.
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are
free-running, and during READs, edge-aligned with data output from the RLDRAM.
QKx# is ideally 180 degrees out of phase with QKx. For the x9 device, all Qs are aligned
with QK0 and QK0#. For the x18 device, QK0 and QK0# are aligned with Q0–Q8 and
QK1 and QK1# are aligned with Q9–Q17.
Data valid: Indicates valid output data and is edge-aligned with QKx and QKx#.
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG
function is not used.
External impedance (25–60Ω): This signal is used to tune the device outputs to the
system data bus impedance. Q output impedance is set to 0.2 × RQ, where RQ is a
resistor from this signal to ground. Connecting ZQ to GND invokes the minimum
impedance mode. Connecting ZQ to Vdd invokes the maximum impedance mode. Refer
to Figure 11 on page 33 to activate this function.
Power supply: Nominally, 2.5V. See Table 6 on page 19 for range.
Power supply: Nominally, 1.8V. See Table 6 on page 19 for range.
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise
immunity. See Table 6 on page 19 for range.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
Power supply: Isolated termination supply. Nominally, Vddq/2. See Table 6 on page 19
for range.
576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
Ball Assignments and Descriptions
©2004 Micron Technology, Inc. All rights reserved.