MT49H32M18CHT-25:A Micron Technology Inc, MT49H32M18CHT-25:A Datasheet - Page 39

• Manufacturer Part Number: MT49H32M18CHT-25:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18CHT-25:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 675mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

READ
Figure 15:
PDF: 09005aef815b2df8/Source: 09005aef811ba111
576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN
READ Command
Read accesses are initiated with a READ command, as shown in Figure 15. Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QKx signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal, QVLD, tran-
sitions from LOW to HIGH. QVLD is also edge-aligned with the QKx signals.
The skew between QK and the crossing point of CK is specified as
skew between QK0 and the last valid data edge generated at the Q signals associated
with QK0 (
valid data edge generated at the Q signals associated with QK1 (
Q9–Q17).
is defined as the skew between either QK differential pair and any output data edge.
After completion of a burst, assuming no other commands have been initiated, output
data (Q) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. Note that if CK/CK# violates the Vid(DC) specification while a READ burst is
occurring, QVLD will remain HIGH until a dummy READ command is issued. The QK
clocks are free-running and will continue to cycle after the read burst is complete. Back-
to-back READ commands are possible, producing a continuous flow of output data.
The data valid window is derived from each QK transition and is defined as:
t
Any READ burst may be followed by a subsequent WRITE command. Figure 26 on
page 50 and Figure 27 on page 50 illustrate the timing requirements for a READ followed
by a WRITE.
ADDRESS
ADDRESS
QHP - (
BANK
REF#
WE#
CK#
CS#
CK
t
QKQ [MAX] + |
t
QKQx is derived at each QKx clock edge and is not cumulative over time.
t
QKQ0 is referenced to Q0–Q8).
576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II
DON’T CARE
BA
A
t
QKQ [MIN]|). See Figure 29 on page 52 for illustration.
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
QKQ1 is the skew between QK1 and the last
©2004 Micron Technology, Inc. All rights reserved.
t
QKQ1 is referenced to
t
CKQK.
Commands
t
QKQ0 is the
t
QKQ