MT49H32M18CHT-25:A Micron Technology Inc, MT49H32M18CHT-25:A Datasheet - Page 18

• Manufacturer Part Number: MT49H32M18CHT-25:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18CHT-25:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 675mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef815b2df8/Source: 09005aef811ba111
576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN
4. Definitions for Idd conditions:
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transi-
6. Idd parameters are specified with ODT disabled.
7. Tests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at nom-
8. Idd tests may use a Vil-to-Vih swing of up to 1.5V in the test environment, but input timing
4b. HIGH is defined as Vin ≥ Vih(AC) MIN.
4d. Floating is defined as inputs at Vref = Vddq/2.
4g. Sequential bank access is defined as the bank address incrementing by one every
4h. Cyclic bank access is defined as the bank address incrementing by one for each com-
4a. LOW is defined as Vin ≤ Vil(AC) MAX.
4e. Continuous data is defined as half the D or Q signals changing between HIGH and LOW
4c. Stable is defined as inputs remaining at a HIGH or LOW level.
4f. Continuous address is defined as half the address signals changing between HIGH and
tions more than once per clock cycle.
inal reference/supply voltage levels, but the related specifications and device operations are
tested for the full voltage range specified.
is still referenced to Vref (or to the crossing point for CK/CK#). Parameter specifications are
tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the range between Vil(AC) and
Vih(AC).
every half clock cycle (twice per clock).
LOW every clock cycle (once per clock).
mand access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – I
©2004 Micron Technology, Inc. All rights reserved.
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RC.
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