SCD240110QCM Intel, SCD240110QCM Datasheet - Page 118

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
1. Only available on Revision H and later.
118
Register Name: CCR
Register Description: Channel Command – Mode 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
1
Note: This command is not available in revisions prior to Revision ‘H’.
Mode 2
Either one or both timers can be cleared with a single command. Note that if the running timer
value is 01h at the time this command is issued, there is a small chance that the timer will expire
and cause a timer interrupt before the command is processed.
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
ClrT1
Bit 6
For Mode 2, this bit must be ‘1’.
Clear Timer 1
General Timer 1 is cleared.
Clear Timer 2
General Timer 2 is cleared.
Clear Receiver Command
This command only affects the receiver. It resets all receiver functions like a combi-
nation of clear channel, initialize channel and enable receiver commands. ClrRcv
clears the receive FIFO and clears receive status in the CSR register, except for the
RcvEn bit. ClrRcv clears the receive DMA buffer status in A/BRBSTS and receive
status in DMABSTS. Clearing the 2401own bits in both Receive Buffer Status reg-
isters means that DMA buffers must be returned to the CD2401 before receive trans-
fers can begin again.
For Synchronous modes, this command puts the receiver back into SYN/Flag Hunt
mode.
Reserved – must be ‘0’.
ClrT2
Bit 5
ClrRcv
Bit 4
0
1
Bit 3
0
Bit 2
0
Motorola Hex Address: x’13
Bit 1
Intel Hex Address: x’10
0
Datasheet
Bit 0
0