SCD240110QCM Intel, SCD240110QCM Datasheet - Page 52

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
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Figure 8. Receiver A and B Buffers
NOTE: The number of bits in each register is shown in parentheses (). Buffer A and buffer B do
Example 1
Receive a frame from channel 1 — no chaining.
1. The host must first make a receive buffer available before a frame can be received. Thus, the
2. The host sets up the starting address — ARBADR and the buffer byte count — ARBCNT.
3. The host then gives the buffer to the CD2401 by setting the 2401own bit (ARBSTS[0])). This
4. The Rbusy bit (DMABSTS[0]) for channel 1 is ‘0’ until a frame starts to be received. When
5. At the end of the received frame, the CD2401 tests for the correct end-of-frame delimiter and
6. The CD2401 sets the EOB and EOF bits. This notifies the host that the end of the buffer and
host checks the Nrbuf bit (DMABSTS[1]) for channel 1 to determine which buffer is next. In
this example, Nrbuf set to ‘0’ indicates buffer A is used next.
When the host writes the count — ARBCNT, the host has defined the size limit for the buffer.
notifies the CD2401 that it is now alright to write received.
frame data starts coming in, the CD2401 sets Nrbuf to notify the host that buffer B is next. As
data bytes are written into the buffer, the current buffer pointer (RCBADR) is updated by the
CD2401.
CRC. When the received frame is complete, the CD2401 clears the Rbusy bit. In this example,
there is no receive chaining, so the received frame byte count is less than or equal to the buffer
size count (ARBCNT). The CD2401 writes the value of the actual received byte count into the
same register — ARBCNT. (Note that the host has written the maximum buffer size in
ARBCNT when the buffer is given to the CD2401. But when the buffer is returned to the host,
the CD2401 has written the actual byte count of the received buffer into ARBCNT.)
frame have been reached. The CD2401 also clears the 2401own bit to return the buffer to the
host.
CD2401 TRANSMIT
not need to be the same length.
DMA REGISTERS
(Currently using Buffer A)
ARBADR (32)
RCBADR (32)
BRBADR (32)
ARBCNT (16)
BRBCNT (16)
ARBSTS (8)
BRBSTS (8)
(Status Register)
(Status Register)
Starting Address
Starting Address
Buffer Byte Count
Current Address
Buffer Byte Count
PHYSICAL
MEMORY
Receiver
Receiver
Buffer
Buffer
A
B
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