SCD240110QCM Intel, SCD240110QCM Datasheet - Page 54

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
5.4.7.1
5.4.7.2
5.4.7.3
54
Buffer Allocation
The CD2401 contains two DMA descriptors that can be loaded by the CPU to specify transmit
buffers. These descriptors are designated A and B, and each consists of a 32-bit address (A/
BTBADR), a 16-bit count (A/BTBCNT), and an 8-bit status (A/BTBSTS).
The Status register contains an Ownership Status bit (2401own). When this bit is set, the CD2401
owns the descriptor, it should not be written to by the CPU. When the bit is clear, the descriptor is
owned by the CPU.
When DMA is selected and the channel is enabled, the CD2401 waits for ownership of buffer A.
When ownership of A is given by setting the 2401own bit, the buffer is transmitted and the
ownership bit is cleared. The CD2401 waits for ownership of buffer B; this process continues,
toggling between the two buffer descriptors.
The DMABSTS register contains a status bit (NtBuf) that informs the CPU of the next buffer to
transmit to ensure that the CPU and CD2401 stay in synchronization. This procedure ensures that a
pipeline of data is available for the CD2401 to send, maximizing the bandwidth utilization and
minimizing the possibility of underruns.
Interrupts for Transmit DMA Buffers
Two types of transmit interrupts are available in DMA mode; they are enabled by the IER and
controlled by the TxD and TxMpty bits.
When the TxMpty interrupt is enabled, interrupts are generated when there is no transmit data
available to send. For example, the TxMpty interrupt can be used by the CPU to determine when
line turn-around can occur on half-duplex lines.
Normally, the TxD interrupt indicates the end of each transmit buffer. The interrupt is scheduled
internally when the last data is read from the transmit buffer into the FIFO.
Because only one interrupt is generated for each buffer, the TxD bit (IER[0]) can be left
permanently enabled. If interrupts are required selectively for individual buffers, the INTR bit (A/
BTBSTS[1]) registers can selectively enable interrupts.
Chained Buffers
In Synchronous modes when the frame size exceeds the maximum buffer size, a frame can be
transmitted from a number of separate buffers. This is achieved simply by not setting the EOF bit
(A/BTBSTS[6]) until the last buffer of the frame. The CD2401 transmits the buffers as one frame;
it appends the CRC only when all the data is transmitted from the buffer with the EOF flag set.
If the above procedure for allocating buffers is used, the CPU has the transmission time of the last
buffer to allocate the next to avoid possible underrun. The EOF bit (TISR[6]) is set for the interrupt
associated with the last buffer.
Figure 9
illustrates this procedure.
Datasheet