IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 50
IDT82V3355TF
Manufacturer Part Number
IDT82V3355TF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V3355TF.pdf
(135 pages)
Specifications of IDT82V3355TF
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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Table 35: Register List and Map (Continued)
Programming Information
IDT82V3355
Address
(Hex)
4A
4B
4E
41
42
44
45
47
4F
50
51
52
53
54
55
56
57
58
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
IN1_IN2_CMOS_STS - CMOS Input
Clock 1 & 2 Status
IN1_IN2_DIFF_STS - Differential Input
Clock 1 & 2 Status
IN3_CMOS_STS - CMOS Input Clock
3 Status
INPUT_VALID1_STS - Input Clocks
Validity 1
INPUT_VALID2_STS - Input Clocks
Validity 2
PRIORITY_TABLE1_STS - Priority
Status 1 *
PRIORITY_TABLE2_STS - Priority
Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected
Input Clock Configuration
T4_INPUT_SEL_CNFG - T4 Selected
Input Clock Configuration
OPERATING_STS - DPLL Operating
Status
T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration
T4_OPERATING_MODE_CNFG - T4
DPLL Operating Mode Configuration
T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth &
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth &
Damping Factor Configuration
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
Register Name
EX_SYNC
_ALARM_
T0_DPLL_LOCKED_DAMPING[2:0]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_ACQ_DAMPING[2:0]
MON
Bit 7
HIGHEST_PRIORITY_VALIDATED[3:0]
-
-
-
-
-
-
-
-
-
-
T0 / T4 DPLL State Machine Control Registers
T0 / T4 DPLL & APLL Configuration Registers
T0 / T4 DPLL Input Clock Selection Registers
IN2_CMOS
T4_LOCK_
IN2_DIFF_
FREQ_HA
T4_DPLL_
_FREQ_H
ARD_ALA
RD_ALAR
T0_APLL_PATH[3:0]
LOCK
Bit 6
RM
T0
M
-
-
-
-
-
-
-
IN2_CMOS
SOFT_FRE
_NO_ACTI
IN2_DIFF_
NO_ACTIV
T0_FOR_T
ITY_ALAR
T0_DPLL_
Q_ALARM
VITY_ALA
IN2_DIFF
Bit 5
RM
50
M
4
-
-
-
-
-
-
IN2_CMOS
SOFT_FRE
IN2_DIFF_
T4_TEST_
K_ALARM
PH_LOCK
T4_DPLL_
Q_ALRAM
_PH_LOC
IN_FREQ_VALUE[7:0]
IN1_DIFF IN2_CMOS IN1_CMOS
_ALARM
T0_PH
Bit 4
-
-
-
-
-
-
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
T0_ETH_OBSAI_16E1_
T0_DPLL_
LOCK
Bit 3
T0_DPLL_LOCKED_BW[4:0]
16T1_SEL[1:0]
T0_DPLL_START_BW[4:0]
-
-
-
-
-
-
CURRENTLY_SELECTED_INPUT[3:0]
T0_DPLL_ACQ_BW[4:0]
IN_FREQ_READ_CH[3:0]
IN1_CMOS
IN3_CMOS
SYNCHRONOUS ETHERNET WAN PLL
IN1_DIFF_
FREQ_HA
T0_DPLL_OPERATING_MODE[2:0]
_FREQ_H
ARD_ALA
RD_ALAR
_FREQ_H
ARD_ALA
T0_INPUT_SEL[3:0]
T4_INPUT_SEL[3:0]
Bit 2
RM
RM
T0_OPERATING_MODE[2:0]
T4_OPERATING_MODE[2:0]
M
-
]
IN1_CMOS
IN3_CMOS
_NO_ACTI
IN1_DIFF_
NO_ACTIV
_NO_ACTI
ITY_ALAR
VITY_ALA
VITY_ALA
T0_12E1_24T1_E3_T3
Bit 1
RM
RM
M
-
-
_SEL[1:0]
IN1_CMOS
IN3_CMOS
IN3_CMOS
IN1_DIFF_
K_ALARM
PH_LOCK
K_ALARM
_PH_LOC
_PH_LOC
_ALARM
Bit 0
-
May 19, 2009
Reference
Page
P 80
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