IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 52

• Manufacturer Part Number: IDT82V3355TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3355TF

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 35: Register List and Map (Continued)
6.2
6.2.1
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
Programming Information
IDT82V3355
Address
Address: 00H
Type: Read
Default Value: 10001000
Address: 01H
Type: Read
Default Value: 00010001
(Hex)
7A
7B
7C
7D
73
74
78
7 - 0
7 - 0
Bit
Bit
ID15
ID7
OUT2_INV_CNFG - Output Clock 2
Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
& Multiframe Sync Output Configura-
tion
PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
PHASE_OFFSET[7:0]_CNFG - Phase
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase
Offset Configuration 2
SYNC_MONITOR_CNFG - Sync Mon-
itor Configuration
SYNC_PHASE_CNFG - Sync Phase
Configuration
7
7
REGISTER DESCRIPTION
GLOBAL CONTROL REGISTERS
Register Name
ID[15:8]
ID[7:0]
Name
Name
ID14
ID6
6
6
Refer to the description of the ID[15:8] bits (b7~0, 01H).
The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3355.
ID13
ID5
IN_2K_4K_
_WINDOW
IN_NOISE
PH_OFFS
SYNC_BY
5
5
8K_INV
ET_EN
PASS
Bit 7
-
-
Synchronization Configuration Registers
PBO & Phase Offset Control Registers
8K_EN
Bit 6
-
-
-
-
ID12
ID4
SYNC_MON_LIMT[2:0]
4
4
PH_MON_
2K_EN
Bit 5
SYNC_PH3[1:0]
EN
52
-
-
2K_8K_PU
PH_MON_
ID11
L_POSITI
ID3
PBO_EN
3
3
Bit 4
PH_OFFSET[7:0]
ON
Description
Description
-
-
8K_INV
Bit 3
SYNC_PH2[1:0]
-
-
-
ID10
ID2
2
2
PH_TR_MON_LIMT[3:0]
SYNCHRONOUS ETHERNET WAN PLL
OUT2_INV
8K_PUL
Bit 2
-
-
2K_INV
ID1
ID9
1
1
Bit 1
PH_OFFSET[9:8]
SYNC_PH1[1:0]
-
-
2K_PUL
Bit 0
-
-
May 19, 2009
ID0
ID8
0
0
Reference
P 106
P 107
P 108
P 109
P 108
P 110
P 111
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