MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 28

• Manufacturer Part Number: MT46H8M32LFB5-6IT:H
• Description: MICMT46H8M32LFB5-6_IT:H MDDDR
• Manufacturer: Micron Technology Inc

PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
26. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
27. The maximum limit for this parameter is not a device limit. The device will operate with
28. At least 1 clock cycle is required during
29. Clock must be toggled a minimum of two times during the
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were
previously progress on the bus. If a previous WRITE was in progress, DQS could be HIGH
during this time, depending on
a greater value for this parameter, but system performance (bus turnaround) will de-
grade accordingly.
Electrical Specifications – AC Operating Conditions
28
256Mb: x16, x32 Mobile LPDDR SDRAM
t
DQSS.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
WR time when in auto precharge mode.
t
XSR period.
© 2008 Micron Technology, Inc. All rights reserved.