MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 93
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MT46H8M32LFB5-6IT:H
Manufacturer Part Number
MT46H8M32LFB5-6IT:H
Description
MICMT46H8M32LFB5-6_IT:H MDDDR
Manufacturer
Micron Technology Inc
Datasheet
1.MT46H8M32LFB5-6ITH.pdf
(96 pages)
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Clock Change Frequency
Figure 53: Clock Stop Mode
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Command
DQ, DQS
Address
CK#
CKE
CK
Notes:
One method of controlling the power efficiency in applications is to throttle the clock
that controls the device. The clock can be controlled by changing the clock frequency or
stopping the clock.
The device enables the clock to change frequency during operation only if all timing pa-
rameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be
completed before entering clock stop mode; this includes the following timings:
t
must be complete. (See READ Operation and WRITE Operation.)
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued.
RP,
Exit clock stop mode
1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before
2. Any valid command is supported; device is not in clock suspend mode.
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RFC,
issuing any valid command.
NOP
Ta1
t
MRD,
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t
WR, and
CMD
Valid
Ta2
2
t
RPST. In addition, any READ or WRITE burst in progress
93
256Mb: x16, x32 Mobile LPDDR SDRAM
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CMD
Tb3
Valid
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
All DRAM activities must be complete
Tb4
NOP
Clock Change Frequency
Enter clock stop mode
© 2008 Micron Technology, Inc. All rights reserved.
NOP
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Don’t Care
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RCD,