MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 79

• Manufacturer Part Number: MT46H8M32LFB5-6IT:H
• Description: MICMT46H8M32LFB5-6_IT:H MDDDR
• Manufacturer: Micron Technology Inc

Figure 42: WRITE-to-PRECHARGE – Interrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
1
5
6
5
6
5
6
WRITE
Bank a,
Col b
T0
Notes:
2
t
t
t
DQSS
DQSS
DQSS
1. An interrupted burst of 8 is shown; two data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4.
5. DQS is required at T4 and T4n to register DM.
6. D
D
b
IN
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
T1
D
IN
b
IN
b = data-in for column b.
b + 1
D
D
b
IN
IN
T1n
b + 1
D
IN
b + 1
D
IN
NOP
T2
T2n
79
t
WR
NOP
T3
256Mb: x16, x32 Mobile LPDDR SDRAM
4
T3n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
(a or all)
PRE
T4
Bank
3
Don’t Care
T4n
T5
NOP
© 2008 Micron Technology, Inc. All rights reserved.
WRITE Operation
Transitioning Data
T6
NOP