EPM570F256I5N Altera, EPM570F256I5N Datasheet - Page 73

• Manufacturer Part Number: EPM570F256I5N
• Description: IC MAX II CPLD 570 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570F256I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 160
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 8.7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 160
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of I/o's: 160
• Propagation Delay: 8.7ns
• Global Clock Setup Time: 1.9ns
• Frequency: 201.1MHz
• Supply Voltage Range: 2.375V To 2.625V, 3V To 3.6V
• Operating Temperature Range: -40°C To +100°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1399; EPM570F256I5N

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)
© August 2009 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
Symbol
DDS
DDH
DP
PB
BP
PP M X
AE
EB
BE
EPM X
DCO
Data register data in
setup to data register
clock
Data register data in
hold from data
register clock
Program signal to
data clock hold time
Maximum delay
between program
rising edge to UFM
busy signal rising
edge
Minimum delay
allowed from UFM
busy signal going low
to program signal
going low
Maximum length of
busy pulse during a
program
Minimum erase signal
to address clock hold
time
Maximum delay
between the erase
rising edge to the
UFM busy signal
rising edge
Minimum delay
allowed from the UFM
busy signal going low
to erase signal going
low
Maximum length of
busy pulse during an
erase
Delay from data
register clock to data
register output
Parameter
Min
–3 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
Max
960
100
960
500
—
—
—
—
—
—
5
MAX II / MAX IIG
Min
–4 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
Max
960
100
960
500
—
—
—
—
—
—
5
Min
–5 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
Max
960
100
960
500
—
—
—
—
—
—
5
Min Max Min Max Min Max
–6 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
960
100
960
500
—
—
—
—
—
—
5
–7 Speed
20
20
—
20
—
—
20
—
—
MAX IIZ
0
0
Grade
960
100
960
500
—
—
—
—
—
—
5
MAX II Device Handbook
–8 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
960
100
960
500
—
—
—
—
—
—
5
Unit
ms
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
5–15