EPM570F256I5N Altera, EPM570F256I5N Datasheet - Page 76

• Manufacturer Part Number: EPM570F256I5N
• Description: IC MAX II CPLD 570 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570F256I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 160
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 8.7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 160
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of I/o's: 160
• Propagation Delay: 8.7ns
• Global Clock Setup Time: 1.9ns
• Frequency: 201.1MHz
• Supply Voltage Range: 2.375V To 2.625V, 3V To 3.6V
• Operating Temperature Range: -40°C To +100°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1399; EPM570F256I5N

5–18
External Timing Parameters
Table 5–23. EPM240 Global Clock External I/O Timing Parameters
MAX II Device Handbook
Symbol
t
t
t
t
t
t
t
t
PD1
PD2
SU
H
CO
CH
CL
CNT
Worst case
pin-to-pin
delay
through 1
look-up table
(LUT)
Best case
pin-to-pin
delay
through
1 LUT
Global clock
setup time
Global clock
hold time
Global clock
to output
delay
Global clock
high time
Global clock
low time
Minimum
global clock
period for
16-bit
counter
Parameter
f
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in
For more information about each external timing parameters symbol, refer to the
Understanding Timing in MAX II Devices
Table 5–23
Condition
10 pF
10 pF
10 pF
—
—
—
—
—
shows the external I/O timing parameters for EPM240 devices.
Min
166
166
1.7
2.0
3.3
—
—
–3 Speed
0
Grade
Max
4.7
3.7
4.3
—
—
—
—
—
MAX II / MAX IIG
Table 5–27
Min
216
216
2.2
2.0
4.0
—
—
–4 Speed
0
Grade
Max
6.1
4.8
5.6
—
—
—
—
—
through
Min
266
266
2.7
2.0
5.0
—
—
–5 Speed
0
(Part 1 of 2)
chapter in the MAX II Device Handbook.
Grade
Table
Max
7.5
5.9
6.9
—
—
—
—
—
5–31.
Min
253
253
2.4
2.0
5.4
—
—
–6 Speed
0
Grade
Chapter 5: DC and Switching Characteristics
Max
7.9
5.8
6.6
—
—
—
—
—
© August 2009 Altera Corporation
Min
335
335
4.1
2.0
8.1
—
—
Timing Model and Specifications
–7 Speed
0
MAX IIZ
Grade
Max
12.0
7.8
8.1
—
—
—
—
—
Min
339
339
4.6
2.0
8.4
—
—
–8 Speed
0
Grade
Max
14.0
8.5
8.6
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ps
ps
ns