EPM570F256I5N Altera, EPM570F256I5N Datasheet - Page 74

• Manufacturer Part Number: EPM570F256I5N
• Description: IC MAX II CPLD 570 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570F256I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 160
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 8.7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 160
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of I/o's: 160
• Propagation Delay: 8.7ns
• Global Clock Setup Time: 1.9ns
• Frequency: 201.1MHz
• Supply Voltage Range: 2.375V To 2.625V, 3V To 3.6V
• Operating Temperature Range: -40°C To +100°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1399; EPM570F256I5N

5–16
Table 5–21. UFM Block Internal Timing Microparameters (Part 3 of 3)
Figure 5–3. UFM Read Waveforms
MAX II Device Handbook
t
t
t
t
Symbol
OE
RA
OSC S
OSC H
Delay from data
register clock to data
register output
Maximum read
access time
Maximum delay
between the
OSC_ENA rising
edge to the
erase/program signal
rising edge
Minimum delay
allowed from the
erase/program signal
going low to
OSC_ENA signal
going low
Parameter
OSC_ENA
Program
DRDout
DRShft
ARShft
DRDin
ARClk
ARDin
DRClk
Erase
Figure 5–3
UFM block timing parameters shown in
Busy
t
t
ASU
ADS
through
Min
180
250
250
–3 Speed
—
Grade
t
ACLK
Max
—
65
—
—
9 Address Bits
Figure 5–5
MAX II / MAX IIG
Min
180
250
250
–4 Speed
—
Grade
Max
—
65
—
—
t
t
ADH
show the read, program, and erase waveforms for
AH
t
DCO
t
DSS
Min
180
250
250
–5 Speed
—
Grade
t
DCLK
Table
Max
—
65
—
—
16 Data Bits
5–21.
Min Max Min Max Min Max
180
250
250
–6 Speed
—
Grade
Chapter 5: DC and Switching Characteristics
—
65
—
—
t
DSH
180
250
250
–7 Speed
—
MAX IIZ
© August 2009 Altera Corporation
Grade
Timing Model and Specifications
—
65
—
—
180
250
250
–8 Speed
—
Grade
—
65
—
—
Unit
ns
ns
ns
ns