AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 12

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS SLAVE
Use these specifications for bus master access to a slave’s IOP registers or internal memory in multiprocessor memory space. The bus
master must meet these bus slave timing requirements.
Table 11. Specifications
Parameter
Timing Requirements:
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
1
2
3
SADRI
HADRI
SRWLI
HRWLI
RWHPI
SDATWH
HDATWH
SDDATO
DATTR
DACKAD
ACKTR
t
4 + DT/8.
See the
t
setup times greater than 19 + 3 DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match responds with ACK regardless
of the state of MMSWS or strobes. A slave three-states ACK every cycle with t
SRWLI
DACKAD
(min) = 9.5 + 5 DT/16 when the multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3 DT/4. If the address and SW inputs have
System Hold Time Calculation Example
WRITE ACCESS
ADDRESS
READ ACCESS
Address, SW Setup before CLKIN
Address, SW Hold before CLKIN
RD/WR Low Setup before CLKIN
RD/WR Low Hold after CLKIN
RD/WR Pulse High
Data Setup before WR High
Data Hold after WR High
Data Delay after CLKIN
Data Disable after CLKIN
ACK Delay after Address, SW
ACK Disable after CLKIN
CLKIN
(OUT)
DATA
DATA
ACK
(IN)
SW
WR
RD
3
2
3
section for the calculation of hold times given capacitive and dc loads.
1
t
SDDATO
Figure 10. Synchronous Read/Write—Bus Slave
Min
15.5 + DT/2
9.5 + 5 DT/16
−3.5 − 5 DT/16
3
5.5
1.5
0 − DT/8
−1 − DT/8
t
DACKAD
Rev. B | Page 12 of 48
ACKTR
.
t
5 V
SADRI
Max
4.5 + DT/2
+8 + 7 DT/16
20 + 5 DT/16
8 − DT/8
10
+7 − DT/8
t
t
SRWLI
SRWLI
t
HADRI
t
SDATWH
Min
15.5 + DT/2
9.5 + 5 DT/16
−3.25 − 5 DT/16
3
5.5
1.5
0 − DT/8
−1 − DT/8
t
t
t
HRWLI
HDATWH
HRWLI
t
t
ACKTR
DATTR
3.3 V
Max
4.5 + DT/2
+8 + 7 DT/16
20.25 + 5 DT/16
8 − DT/8
10
+7 − DT/8
t
RWHPI
t
RWHPI
SRWLI
(min) =
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns