AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 9

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

MEMORY WRITE—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 9. Specifications
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
W = number of wait states specified in WAIT register × t
H = t
I = t
1
2
3
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
DDWR
WDE
SADADC
ACK delay/setup: User must meet t
For MS x, SW , BMS , the falling edge is referenced.
See the
CK
CK
, if a bus idle cycle occurs, as specified in WAIT register; otherwise, I = 0.
, if an address hold cycle occurs, as specified in WAIT register; otherwise, H = 0.
System Hold Time Calculation Example
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR
De-asserted
Address, Selects to WR Low
WR Pulse Width
Data Setup before WR High
Address Hold after WR De-asserted
Data Disable after WR De-asserted
WR High to WR, RD, DMAGx Low
Data Disable before WR or RD Low
WR Low to Data Enabled
Address, Selects to ADRCLK High
RD, DMAG
ADDRESS
MSx, SW
ADRCLK
DATA
(OUT)
BMS
ACK
WR
2
DAAK
, t
1
DSAK
t
2
SADADC
, or synchronous specification, t
t
section for the calculation of hold times given capacitive and dc loads.
DAWL
1, 2
2
3
t
DAAK
CK
Min
16.5 + 15 DT/16 + W
2.5 + 3 DT/8
12 + 9 DT/16 + W
6.5 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
8 + 7 DT/16 + H
4.5 + 3 DT/8 + 1
−1.5 + DT/16
−0.5 + DT/4
.
t
DSAK
Figure 8. Memory Write—Bus Master
t
WDE
Rev. B | Page 9 of 48
SACKC
t
DAWH
5 V
.
Max
13.5 + 7 DT/8 + W
8 + DT/2 + W
6.5 + DT/16 + H
t
WW
t
DDWH
Min
16.5 + 15 DT/16 + W
2.5 + 3 DT/8
12 + 9 DT/16 + W
6.5 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
8 + 7 DT/16 + H
4.5 + 3 DT/8 + 1
−1.5 + DT/16
−0.5 + DT/4
t
DATRWH
t
DWHA
t
WWR
t
3.3 V
AD14060/AD14060L
DDWR
Max
13.5 + 7 DT/8 + W
8 + DT/2 + W
6.5 + DT/16 + H
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns