AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 46

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AD14060BF-4

Manufacturer Part Number
AD14060BF-4
Description
IC DSP CMOS 32BIT 308CQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of AD14060BF-4

Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
2MB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
308-CQFP
Device Core Size
32b
Architecture
Enhanced Harvard
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
1.9073535156MB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
308
Package Type
CQFP
Lead Free Status / Rohs Status
Not Compliant
AD14060/AD14060L
PCB LAYOUT GUIDELINES
The drawing in Figure 40 assumes that the trim/form tooling
described previously is used. These recommendations are
provided for user convenience and are PCB layout guidelines
only, based on standard practice. PCB pad footprint geometries
and placement are illustrated.
0.025 (0.635) MIN
THICKNESS 5 MILS
THERMOPLASTIC
SILICON DIE
Dimensions shown in inches and (millimeters)
Figure 40. PC Board Component Footprint
19 MILS
BASE
THIS IS A PC BOARD COMPONENT FOOTPRINT,
SIG2
SIG3
SIG4
SIG5
GND
V
DD
NOT THE PACKAGE OUTLINE.
2.060 (52.324) 4 PLACES
2.260 (57.404) 4 PLACES
1.9000 (48.26) 4 PLACES
KOVAR LID
0.015 MILS
KOVAR SEAL RING
HEIGHT = 50 MILS
0.025 (0.635) MIN
Figure 41. Co-Fired Packaged Profile
0.015
(0.381)
0.025
(0.635)
Rev. B | Page 46 of 48
Thermal Characteristics
The AD14060/AD14060L is packaged in a 308-lead ceramic
quad flatpack (CQFP). The package is optimized for thermal
conduction through the core (base of the package) down to the
mounting surface. The AD14060/AD14060L is specified for a
case temperature (T
attachment material should be such that T
Thermal Cross-Section
The following data, together with the detailed mechanical
drawings in Figure 43, allows the designer to construct simple
thermal models for further analysis within targeted systems.
The top layer of the package, where the die are mounted, is a
metal V
metal planes and routing layers is estimated in Table 27. The
layers are shown in Figure 41.
Table 26. Thermal Conductivity
Material
Ceramic
Kovar™
Tungsten
Thermoplastic
Silicon
Table 27. Metal Coverage per Layer
Layer
V
SIG2
SIG3
GND
SIG4
SIG5
BASE
DD
θ
JC
DD
= 0.36°C/W
layer. The approximate metal area coverage from the
CASE
Thermal Conductivity (W/cm°C)
0.18
0.14
1.78
0.03
1.45
% Metal (1 Mil Thick)
88
16
14
91
15
13
95
). Design of the mounting surface and
SURFACE
CERAMIC LAYER 28 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CASE
is not exceeded.

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