AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 18

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
DMA HANDSHAKE
These specifications describe the three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For handshake
mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the
ADDR
WR , MS
read/write—bus master timing specifications for ADDR
Table 15. Specifications
Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = number of wait states specified in WAIT register × t
HI = t
1
2
3
4
SDRLC
SDRHC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
VDATDGH
DATRDGH
DGWRL
DGWRH
DGWRR
DGRDL
DRDGH
DGRDR
DGWR
DADGH
DDGHA
Required only for recognition in the current cycle.
t
can be driven t
t
equals the number of extra cycles that the access is prolonged.
See the
SDATDGL
VDATDGH
CK
, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
31-0
is the data setup requirement, if DMAR x is not being used to hold off completion of a write. Otherwise, if DMAR x low holds off completion of the write, the data
is valid, if DMAR x is not being used to hold off completion of a read. If DMAR x is used to prolong the read, then t
System Hold Time Calculation Example
3-0
, RD , WR , SW , PAGE, MS
, and ACK (not DMAG ). For paced master mode, the memory read—bus master, memory write—bus master, and synchronous
DMARx Low Setup before CLKIN
DMARx High Setup before CLKIN
DMAR x Width Low (Nonsynchronous)
Data Setup after DMAGx Low
Data Hold after DMAGx High
Data Valid after DMAGx High
DMAGx Low Edge to Low Edge
DMAGx Width High
DMAGx Low Delay after CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay after CLKIN
Data Valid before DMAGx High
Data Disable after DMAGx High
WR Low before DMAGx Low
DMAGx Low before WR High
WR High before DMAGx High
RD Low before DMAGx Low
RD Low before DMAGx High
RD High before DMAGx High
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
Address/Select Hold after DMAGx High
DATDRH
after DMAR x is brought high.
3-0
, ACK, and DMAG signals. For paced master mode, the data transfer is controlled by ADDR
2
2
section for the calculation of hold times given capacitive and dc loads.
3
4
1
1
CK
.
Min
5
5
6
2
23 + 7 DT/8
6
9 + DT/4
6 + 3 DT/8
12 + 5 DT/8
−2 − DT/8
7.5 + 9 DT/16
−1
−0.5
9.5 + 5 DT/8 + W
0.5 + DT/16
−0.25
11 + 9 DT/16 + W
0
4.5 + 3 DT/8 + HI
16 + DT
−1.5
31-0
, RD , WR , MS
Rev. B | Page 18 of 48
5 V
3-0
, SW , PAGE, DATA
Max
9 + 5 DT/8
15.5 + 7 DT/8
16 + DT/4
+7 − DT/8
+7.5
+2.5
3.5 + DT/16
+2.5
3.5
Min
5
5
6
2
23 + 7 DT/8
6
9 + DT/4
6 + 3 DT/8
12 + 5 DT/8
−2 − DT/8
7.5 + 9 DT/16
−1
−0.75
9.5 + 5 DT/8 + W
0.5 + DT/16
0
11 + 9 DT/16 + W
0
4.5 + 3 DT/8 + HI
16 + DT
−1.5
47-0
, and ACK also apply.
VDATDGH
= 7.5 + 9 DT/16 + (n × t
3.3 V
Max
9 + 5 DT/8
15.5 + 7 DT/8
16 + DT/4
+7 − DT/8
+7.5
+2.5
3.5 + DT/16
2.5
3.5
CK
), where n
31-0
, RD ,
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns