AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 15

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

ASYNCHRONOUS READ/WRITE—HOST TO AD14060/AD14060L
Use these specifications for asynchronous host processor access to an AD14060/AD14060L, after the host has asserted CS and HBR (low).
After HBG is returned by the AD14060/AD14060L, the host can drive the RD and WR pins to access the AD14060/AD14060L’s internal
memory or IOP registers. HBR and HBG are assumed low for this timing.
Table 13. Specifications
Parameter
Read Cycle
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Write Cycle
Timing Requirements:
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
1
SADRDL
HADRDH
WRWH
DRDHRDY
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
SCSWRL
HCSWRH
SADWRH
HADWRH
WWRL
WRWH
DWRHRDY
SDATWH
HDATWH
DRDYWRL
RDYPWR
SRDYCK
Not required, if RD and address are valid t
goes low or by t
during asynchronous host accesses, see the ADSP-2106x SHARC User’s Manual.
Address Setup/CS Low before RD Low
Address Hold/CS Hold Low after RD
RD/WR High Width
RD High Delay after REDY (O/D) Disable
RD High Delay after REDY (A/D) Disable
Data Valid before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay after RD Low
REDY (O/D) or (A/D) Low Pulse Width for Read
Data Disable after RD High
CS Low Setup before WR Low
CS Low Hold after WR High
Address Setup before WR High
Address Hold after WR High
WR Low Width
RD/WR High Width
WR High Delay after REDY (O/D) or (A/D) Disable
Data Setup before WR High
Data Hold After WR High
REDY (O/D) or (A/D) Low Delay after WR/CS Low
REDY (O/D) or (A/D) Low Pulse Width for Write
REDY (O/D) or (A/D) Disable to CLKIN
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be driven
REDY (O/D)
REDY (A/D)
CLKIN
HBGRCSV
after HBG goes low. For first access after HBR is asserted, ADDR
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
1
Figure 12. Synchronous REDY Timing
Rev. B | Page 15 of 48
Min
0.5
0.5
6
0
0
1.5
45 + DT
1.5
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
15
0 + 7 DT/16
5 V
t
Max
11
9
11
8 + 7 DT/16
SRDYCK
31–0
must be a non-MMS value 1/2 t
Min
0.5
0.5
6
0
0
1.5
45 + DT
1.5
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
15
0 + 7 DT/16
AD14060/AD14060L
3.3 V
Max
13.5
9.5
13.5
8 + 7 DT/16
CLK
before RD or WR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns