AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 32

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
Pin
FLAG1
FLAGy2
IRQy2-0
DMAR1
DMAR2
DMAG1
DMAG2
LyxCLK
LyxDAT3-0
LyxACK
EBOOTA
LBOOTA
BMSA
EBOOTBCD
LBOOTBCD
BMSBCD
TIMEXPy
CLKIN
RESET
TCK
TMS
Type
I/O/A
I/O/A
I/A
I/A
I/A
O/T
O/T
I/O
I/O
I/O
I
I
I/O/T
I
I
I/O/T
O
I
I/A
I
I/S
3
3
1
Function
Flag Pins (FLAG1 common to all SHARCs). This pin is configured via control bits internal to individual ADSP-21060s
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Flag Pins (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Interrupt Request Lines (individual IRQ
triggered or level-sensitive.
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-20160.
Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
down resistor that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
EPROM Boot Select (SHARC_A). When EBOOTA is high, SHARC_A is configured for booting from an 8-bit EPROM.
When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode for SHARC_A. See the following
table. This signal is a system configuration selection that should be hardwired.
Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is low, SHARC_A is
configured for host processor booting or no booting. See the following table. This signal is a system configuration
selection that should be hardwired.
Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTA =
1, LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_A is to begin executing instructions from external memory.
See the following table. This input is a system configuration selection that should be hardwired.
EPROM Boot Select (common to SHARC_B, SHARC_C, SHARC_D). When EBOOTBCD is high, SHARC_B, C, and D are
configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the LBOOTBCD and BMSBCD inputs
determine booting mode for SHARC_B, C, and D. See the following table. This signal is a system configuration
selection that should be hardwired.
LINK Boot (common to SHARC_B, SHARC_C, SHARC_D). When LBOOTBCD is high, SHARC_B, C, and D are configured
for link port booting. When LBOOTBCD is low, SHARC_B, C, and D are configured for host processor booting or no
booting. See the following table. This signal is a system configuration selection that should be hardwired.
Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTBCD
= 1, LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_B, C, and D are to begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
EBOOT
1
0
0
0
0
1
Timer Expired (individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Asserted for four cycles when
the timer is enabled and TCOUNT decrements to 0.
Clock In (common to all SHARCs). External clock input to the AD14060/AD14060L. The instruction cycle rate is equal
to CLKIN. CLKIN cannot be halted, changed, or operated below the minimum specified frequency.
Module Reset (common to all SHARCs). Resets the AD14060/AD14060L to a known state. This input must be
asserted (low) at power-up.
Test Clock (JTAG) (common to all SHARCs). Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG) (common to all SHARCs). Used to control the test state machine. TMS has a 20 kΩ internal
pull-up resistor.
LBOOT
0
0
1
0
1
1
BMS
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
No booting. Processor executes from external memory.
Booting Mode
EPROM (connect BMS to EPROM chip select).
Host processor.
Link port.
Reserved.
Reserved.
Rev. B | Page 32 of 48
2-0
from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Can be either edge-
2
2
. Each LyxDAT pin has a 50 kΩ internal pull-down resistor
. Each LyxCLK pin has a 50 kΩ internal pull-down resistor
2
. Each LyxACK pin has a 50 kΩ internal pull-