XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 153

• Manufacturer Part Number: XC4005L-5PQ100C
• Description: IC 3.3V FPGA 196 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ100C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1121

September 18, 1996 (Version 1.04)
HQ240 Pin
PQ240/
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208
P209
XC4013E
XC4013L
(D0, DIN)
I/O (CS1,
(A0, WS)
(DOUT)
O, TDO
I/O (A3)
I/O (A4)
I/O (A5)
I/O (A6)
SGCK4
PGCK4
(RCLK,
BUSY)
CCLK
N.C.‡
RDY/
VCC
GND
GND
VCC
N.C.
(A1)
I/O,
I/O,
A2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC4020E XC4025E
(D0, DIN)
I/O (CS1,
(A0, WS)
(DOUT)
O, TDO
PGCK4
I/O (A3)
I/O (A4)
I/O (A5)
I/O (A6)
(RCLK,
SGCK4
BUSY)
CCLK
N.C.‡
RDY/
GND
GND
VCC
VCC
N.C.
(A1)
I/O,
I/O,
A2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(D0, DIN)
I/O (CS1,
(A0, WS)
(DOUT)
I/O (A3)
I/O (A4)
I/O (A5)
I/O (A6)
SGCK4
O, TDO
PGCK4
(RCLK,
BUSY)
CCLK
N.C.‡
RDY/
GND
GND
VCC
VCC
(A1)
I/O,
I/O,
A2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC4028EX
XC4028XL
(D0, DIN)
I/O (CS1,
I/O (A21)
I/O (A20)
(A0, WS)
(DOUT)
I/O (A3)
I/O (A6)
O, TDO
I/O (A4)
I/O (A5)
(RCLK,
BUSY)
GCK6
GCK7
GND‡
CCLK
RDY/
GND
GND
VCC
VCC
(A1)
I/O,
I/O,
A2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3/11/96
‡ Pins labelled GND‡ should be connected to Ground if
possible; however, they can be left unconnected if neces-
sary for compatibility with other devices. Pins labelled
N.C.‡ are reserved for Ground connections on future revi-
sions of the device. These pins do not physically connect
to anything on the current device revision. However, they
should be externally connected to Ground if possible.
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
HQ240 Pin
PQ240/
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
P240
XC4013E
XC4013L
I/O (A10) I/O (A10) I/O (A10)
I/O (A11) I/O (A11) I/O (A11)
I/O (A12) I/O (A12) I/O (A12)
I/O (A13) I/O (A13) I/O (A13)
I/O (A14) I/O (A14) I/O (A14)
I/O (A7)
I/O (A8)
I/O (A9)
SGCK1
N.C.‡
(A15)
GND
GND
VCC
VCC
VCC
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC4020E XC4025E
I/O (A7)
I/O (A8)
I/O (A9)
SGCK1
N.C.‡
(A15)
GND
GND
VCC
VCC
VCC
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A7)
I/O (A8)
I/O (A9)
SGCK1
N.C.‡
(A15)
GND
GND
VCC
VCC
VCC
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC4028EX
XC4028XL
I/O (A19)
I/O (A18)
I/O (A10)
I/O (A11)
I/O (A12)
I/O (A13)
I/O (A14)
I/O (A7)
I/O (A8)
I/O (A9)
GND‡
GCK8
(A15)
GND
GND
VCC
VCC
VCC
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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