XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 74

IC 3.3V FPGA 196 CLB'S 100-PQFP

XC4005L-5PQ100C

Manufacturer Part Number
XC4005L-5PQ100C
Description
IC 3.3V FPGA 196 CLB'S 100-PQFP
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet

Specifications of XC4005L-5PQ100C

Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
77
Number Of Gates
5000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-BQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1121

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4005L-5PQ100C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4005L-5PQ100C
Manufacturer:
XILINX
0
XC4000 Series Field Programmable Gate Arrays
Table 24: Pin Functions During Configuration
* XC4000EX only
Notes
4-78
PROGRAM (I)
M2(HIGH) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
CCLK (I)
SERIAL
<1:1:1>
SLAVE
DONE
DIN (I)
DOUT
TMS
TDO
TCK
INIT
TDI
1. A shaded table cell represents a 50 k - 100 k pull-up before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
PROGRAM (I)
M2(LOW) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
CCLK (O)
MASTER
SERIAL
<0:0:0>
DONE
DIN (I)
DOUT
TCK
TMS
TDO
INIT
TDI
RDY/BUSY (O) RDY/BUSY (O)
PROGRAM (I)
M1(HIGH) (I)
M0(HIGH) (I)
M2(LOW) (I)
HDC (HIGH)
LDC (LOW)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
PERIPH-
SYNCH.
CCLK (I)
<0:1:1>
CONFIGURATION MODE <M2:M1:M0>
DONE
DOUT
ERAL
TMS
TDO
TCK
INIT
TDI
PROGRAM (I)
M2(HIGH) (I)
M0(HIGH) (I)
M1(LOW) (I)
HDC (HIGH)
LDC (LOW)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
ASYNCH.
CCLK (O)
PERIPH-
<1:0:1>
CS0 (I)
DONE
DOUT
WS (I)
ERAL
RS (I)
TMS
TDO
TCK
CS1
INIT
TDI
PROGRAM (I)
M2(HIGH) (I)
M1(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
PARALLEL
LDC (LOW)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
CCLK (O)
RCLK (O)
MASTER
<1:1:0>
DOWN
DONE
DOUT
A18*
A19*
A20*
A21*
TMS
TDO
INIT
TCK
A10
A11
A12
A13
A14
A15
A16
A17
TDI
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
PARALLEL UP
PROGRAM (I)
M2(HIGH) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
CCLK (O)
RCLK (O)
MASTER
<1:0:0>
DONE
DOUT
A18*
A19*
A20*
A21*
TCK
TMS
TDO
INIT
A10
A11
A12
A13
A14
A15
A16
A17
TDI
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
September 18, 1996 (Version 1.04)
PROGRAM (I)
M1(HIGH) (I)
M0(HIGH) (I)
M2(LOW) (I)
HDC (HIGH)
LDC (LOW)
EXPRESS
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
CCLK (I)
<0:1:0>
DONE
DOUT
TMS
TDO
TCK
INIT
TDI
SGCK4-GCK5-I/O
PGCK4-GCK6-I/O
SGCK1-GCK7-I/O
PGCK1-GCK8-I/O
ALL OTHERS
OPERATION
PROGRAM
CCLK (I)
TDO-(O)
TMS-I/O
TCK-I/O
TDI-I/O
USER
DONE
(O)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(I)
(I)

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