EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 61

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Periphery Performance
© December 2009
1
Altera Corporation
Table 2–25
Table 2–25. Cyclone III LS Devices JTAG Timing Parameters
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several systems interfacing, for example, the high-speed
I/O interface, external memory interface, and PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are
capable of typical 200 MHz interfacing frequency with 10 pF load.
Your actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 2–26
devices. For more information about the definitions of high-speed timing
specifications, refer to
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes to
(1) The specification shown is for the 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For the 1.8-V
(2) For more information, refer to
JC P
JC H
JC L
JP SU_TDI
JP SU_TM S
JP H
JP CO
JP ZX
JP XZ
JS SU
JS H
JS CO
JS ZX
JS XZ
Symbol
LVTTL/LVCMOS and the 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Table
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
lists the JTAG timing parameters and values for Cyclone III LS devices.
through
2–25:
Table 2–31
“Glossary” on page
“JTAG Waveform”
list the high-speed I/O timing for Cyclone III LS
Parameter
(1)
(1)
(1)
(1)
in
“Glossary” on page
2–26.
(1)
(1)
(Note 2)
2–26.
Cyclone III Device Handbook, Volume 2
(Preliminary)
Min
40
20
20
10
—
—
—
10
—
—
—
2
3
5
Max
—
—
—
—
—
—
16
15
15
—
—
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2–17