EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 137
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
Figure 6–12. Cyclone IV Devices LVDS Interface with True Output Buffer on the Right I/O Banks
BLVDS I/O Standard Support in Cyclone IV Devices
© December 2010 Altera Corporation
Transmitting Device
txout -
txout +
Figure 6–12
LVDS output and input buffers.
Figure 6–13
using two single-ended output buffers and external resistors.
Figure 6–13. LVDS Interface with External Resistor Network on the Top and Bottom I/O
Banks
Note to
(1) R
The BLVDS I/O standard is a high-speed differential data transmission technology
that extends the benefits of standard point-to-point LVDS to multipoint configuration
that supports bidirectional half-duplex communication. BLVDS differs from standard
LVDS by providing a higher drive to achieve similar signal swings at the receiver
while loaded with two terminations at both ends of the bus.
50 Ω
50 Ω
S
Figure
= 120 . R
(Note 1)
LVDS Transmitter
100 Ω
Cyclone IV Device
rxin +
rxin -
6–13:
shows a point-to-point LVDS interface using Cyclone IV devices true
shows a point-to-point LVDS interface with Cyclone IV devices LVDS
Emulated
P
= 170 .
Input Buffer
Family Logic
Cyclone IV Device
Cyclone IV
Device
Array
Resistor Network
R S
R S
R P
Output Buffer
txout +
txout -
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
Cyclone IV Device Handbook, Volume 1
rxin +
rxin -
100 Ω
LVDS Receiver
Receiving Device
6–29
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