EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 339
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Serial RapidIO Mode
Figure 1–60. Transceiver Channel Datapath and Clocking when Configured in Serial RapidIO Mode
Notes to
(1) Optional rate match FIFO.
(2) High-speed recovered clock.
(3) Low-speed recovered clock.
© December 2010 Altera Corporation
Fabric
FPGA
tx_clkout
Figure 1–60
1
:
Serial RapidIO mode provides the non-bonded (×1) transceiver channel datapath
configuration for SRIO protocol implementation. The Cyclone IV GX transceiver
provides the PMA and the following PCS functions:
■
■
Cyclone IV GX transceivers do not have built-in support for some PCS functions such
as pseudo-random idle sequence generation and lane alignment in ×4 bonded
channel configuration. If required, you must implement these functions in a user
logics or external circuits.
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signals, communications, network processes, system memories, and peripheral
devices. The SRIO physical layer specification defines serial protocol running at
1.25 Gbps, 2.5 Gbps, and 3.125 Gbps in either single-lane (×1) or bonded four-lane (×4)
at each line rate. Cyclone IV GX transceivers support single-lane (×1) configuration at
all three line rates. Four ×1 channels configured in Serial RapidIO mode can be
instantiated to achieve one non-bonded ×4 SRIO link. When implementing four ×1
SRIO channels, the receivers do not have lane alignment or deskew capability.
Figure 1–60
Serial RapidIO mode.
8B/10B encoding and decoding
lane synchronization state machine
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
ing
serializer
/2
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
Receiver Channel PCS
rd_clk
Match
FIFO
Rate
(1)
8B/10B Encoder
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
(3)
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(2)
1–59
CDR
low-speed clock
high-speed
clock
CDR clock
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