EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 287
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EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel Datapath
© December 2010 Altera Corporation
K28.5 at time n + 2 is encoded as a positive disparity code group. In the same example,
the current running disparity at time n + 5 indicates that the K28.5 in time n + 6 should
be encoded with a positive disparity. Because tx_forcedisp is high at time n + 6,
and tx_dispval is high, the K28.5 at time n + 6 is encoded as a negative disparity
code group.
Miscellaneous Transmitter PCS Features
The transmitter PCS supports the following additional features:
■
Figure 1–9. Transmitter Polarity Inversion
■
Polarity inversion—corrects accidentally swapped positive and negative signals
from the serial differential link during board layout by inverting the polarity of
each bit. An optional tx_invpolarity port is available to dynamically invert the
polarity of every bit of the 8-bit or 10-bit input data to the serializer in the
transmitter datapath.
1
Bit reversal—reverses the transmit bit order from LSB-to-MSB (default) to
MSB-to-LSB at the input to the serializer. For example, input data to serializer
D[7..0] is rewired to D[0..7] for 8-bit data width, and D[9..0] is rewired to
D[0..9] for 10-bit data width.
feature.
tx_invpolarity is a dynamic signal and might cause initial disparity
errors at the receiver of an 8B/10B encoded link. The downstream system
must be able to tolerate these disparity errors.
Output from transmitter PCS
Figure 1–9
0
1
1
1
0
0
0
1
0
0
MSB
LSB
tx_invpolarity = HIGH
Figure 1–10
shows the transmitter polarity inversion feature.
Converted data output to the
shows the transmitter bit reversal
transmitter serializer
1
0
0
0
1
1
1
0
1
1
Cyclone IV Device Handbook, Volume 2
MSB
LSB
1–7
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