EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 374
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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2–8
Cyclone IV Device Handbook, Volume 2
As shown in
in automatic lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
4. For the receiver operation, after deassertion of busy signal, wait for two parallel
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
between markers 1 and 2).
signals asserted during this time period. After you deassert the pll_areset
signal, the multipurpose PLL starts locking to the input reference clock.
high, deassert the tx_digitalreset signal. At this point, the transmitter is
ready for data traffic.
clock cycles to deassert the rx_analogreset signal.
rx_freqlocked signal of each channel may go high at different times (indicated
by the slashed pattern at marker 7).
has gone high, from that point onwards, wait for at least t
receiver parallel clock to be stable, then deassert the rx_digitalreset signal
(marker 8). At this point, all the receivers are ready for data traffic.
Figure
2–4, perform the following reset procedure for the receiver CDR
Chapter 2: Cyclone IV Reset Control and Power Down
© December 2010 Altera Corporation
LTD_Auto
Transceiver Reset Sequences
time for the
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