EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 400
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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3–10
Figure 3–3. Dynamic Reconfiguration Signals Transition during Offset Cancellation
Notes to
(1) After device power up, the busy signal remains low for the first reconfig_clk cycle.
(2) The busy signal then gets asserted for the second reconfig_clk cycle, when the dynamic reconfiguration controller initiates the offset
(3) The deassertion of the busy signal indicates the successful completion of the offset cancellation process.
Dynamic Reconfiguration Modes
Cyclone IV Device Handbook, Volume 2
cancellation process.
Figure
3–3:
1
reconfig_clk
The gxb_powerdown signal must not be asserted during the offset cancellation
sequence.
Figure 3–3
Functional Simulation of the Offset Cancellation Process
You must connect the ALTGX_RECONFIG instances to the ALTGX instances in your
design for functional simulation. Functional simulation uses a reduced timing model
of the dynamic reconfiguration controller. Therefore, the duration of the offset
cancellation process is 16 reconfig_clk clock cycles for functional simulation only.
The gxb_powerdown signal must not be asserted during the offset cancellation
sequence (for functional simulation and silicon).
When you enable the dynamic reconfiguration feature, you can reconfigure the
following portions of each transceiver channel dynamically, without powering down
the other transceiver channels or the FPGA fabric of the device:
■
■
■
busy
Analog (PMA) controls reconfiguration
Channel reconfiguration
PLL reconfiguration
(1)
shows the timing diagram for a offset cancellation process.
(2)
Chapter 3: Cyclone IV Dynamic Reconfiguration
(3)
© December 2010 Altera Corporation
Dynamic Reconfiguration Modes
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