EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 416
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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3–26
Cyclone IV Device Handbook, Volume 2
Table 3–6
mode in Cyclone IV GX devices.
Table 3–6. Dynamic Reconfiguration Clocking Interface Settings in Channel Reconfiguration Mode
Transmitter core clocking refers to the clock that is used to write the parallel data from
the FPGA fabric into the Transmit Phase Compensation FIFO. You can use one of the
following clocks to write into the Transmit Phase Compensation FIFO:
■
■
Option 1: Share a Single Transmitter Core Clock Between Transmitters
■
■
Dynamic Reconfiguration Channel Internal and Interface Settings
How should the receivers be
clocked?
How should the transmitters be
clocked?
tx_coreclk—you can use a clock of the same frequency as tx_clkout from the
FPGA fabric to provide the write clock to the Transmit Phase Compensation FIFO.
If you use tx_coreclk, it overrides the tx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
tx_clkout—the Quartus II software automatically routes tx_clkout to the
FPGA fabric and back into the Transmit Phase Compensation FIFO.
Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the write clock to the Transmitter Phase
Compensation FIFOs of the remaining channels in the transceiver block.
This option is typically enabled when all the channels of a transceiver block have
the same functional mode and data rate and are reconfigured to the identical
functional mode and data rate.
ALTGX Setting
lists the supported clocking interface settings for channel reconfiguration
Select one of the available options:
■
■
■
Select one of the available options:
■
■
Share a single transmitter core clock between receivers
Use the respective channel transmitter core clocks
Use the respective channel receiver core clocks
Share a single transmitter core clock between transmitters
Use the respective channel transmitter core clocks
Chapter 3: Cyclone IV Dynamic Reconfiguration
Description
© December 2010 Altera Corporation
Dynamic Reconfiguration Modes
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