EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 353

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Loopback
Loopback
Reverse Parallel Loopback
Figure 1–70. PIPE Reverse Parallel Loopback Path
Note to
(1) Grayed-Out Blocks are Not Active in this mode.
© December 2010 Altera Corporation
Fabric
FPGA
Figure 1–70
Transceiver
1
:
Cyclone IV GX devices provide three loopback options that allow you to verify the
operation of different functional blocks in the transceiver channel. The following
loopback modes are available:
■
■
■
In each loopback mode, all transmitter buffer and receiver buffer settings are available
if the buffers are active, unless stated otherwise.
The reverse parallel loopback option is only available for PIPE mode. In this mode,
the received serial data passes through the receiver CDR, deserializer, word aligner,
and rate match FIFO before looping back to the transmitter serializer and transmitted
out through the TX buffer, as shown in
to the FPGA fabric. This loopback mode is compliant with version 2.00 of the
Interface for the PCI Express Architecture
To enable the reverse parallel loopback mode, assert the tx_detectrxloopback
port in P0 power state.
PCIe
hard
IP
reverse parallel loopback (available only for PIPE mode)
serial loopback (available for all modes except PIPE mode)
reverse serial loopback (available for all modes except XAUI mode)
PIPE
IF
(Note 1)
Rx PCS
Match
Reverse parallel
FIFO
Rate
loopback path
Tx PCS
Figure
specification.
Aligner
1–70. The received data is also available
Word
Tx PMA
Serializer
Cyclone IV Device Handbook, Volume 2
Rx PMA
Deserial-
izer
CDR
PHY
1–73