EP3C120F484I7 Altera, EP3C120F484I7 Datasheet - Page 137

• Manufacturer Part Number: EP3C120F484I7
• Description: IC CYCLONE III FPGA 120K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F484I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 283
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 283
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–9. LVPECL DC-Coupled Termination
Differential SSTL I/O Standard Support in the Cyclone III Device Family
Figure 7–10. Differential SSTL Class I Interface
© December 2009
Output Buffer
f
Altera Corporation
LVPECL Transmitter
Figure 7–9
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. The Cyclone III device family supports
differential SSTL-2 and SSTL-18 I/O standards. The differential SSTL I/O standard
requires two differential inputs with an external reference voltage (VREF) as well as an
external termination voltage (VTT) of 0.5 × V
connected. The differential SSTL output standard is only supported at PLL#_CLKOUT
pins using two single-ended SSTL output buffers (PLL#_CLKOUTp and
PLL#_CLKOUTn), with the second output programmed to have opposite polarity. The
differential SSTL input standard is supported on the GCLK pins only, treating
differential inputs as two single-ended SSTL and only decoding one of them.
For more information about the differential SSTL electrical specifications, refer to the
Cyclone III Device I/O Features
Cyclone III LS Device Data Sheet
Figure 7–10
shows the LVPECL DC-coupled termination.
shows the differential SSTL Class I interface.
50
50
chapter and the
chapters.
V
100
TT
CCIO
Cyclone III Device Data Sheet
Cyclone III Device Family
to which termination resistors are
LVPECL Receiver
V
TT
Cyclone III Device Handbook, Volume 1
Receiver
and
7–13