EP3C120F484I7 Altera, EP3C120F484I7 Datasheet - Page 41

• Manufacturer Part Number: EP3C120F484I7
• Description: IC CYCLONE III FPGA 120K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F484I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 283
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 283
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Packed Mode Support
Address Clock Enable Support
© December 2009
Altera Corporation
Figure 3–2
Figure 3–2. Cyclone III Device Family byteena Functional Waveform
Note to
(1) For this functional waveform, New Data mode is selected.
When a byteena bit is deasserted during a write cycle, the old data in the memory
appears in the corresponding data-byte output. When a byteena bit is asserted
during a write cycle, the corresponding data-byte output depends on the setting
chosen in the Quartus
the old data at that location.
Cyclone III device family M9K memory blocks support packed mode. You can
implement two single-port memory blocks in a single block under the following
conditions:
■
■
Cyclone III device family M9K memory blocks support an active-low address clock
enable, which holds the previous address value for as long as the addressstall
signal is high (addressstall = '1'). When you configure M9K memory blocks in
dual-port mode, each port has its own independent address clock enable.
contents at a0
contents at a1
contents at a2
Each of the two independent block sizes is less than or equal to half of the M9K
block size. The maximum data width for each independent block is 18 bits wide.
Each of the single-port memory blocks is configured in single-clock mode. For
more information about packed mode support, refer to
page 3–8
q (asynch)
address
byteena
Figure
inclock
wren
rden
data
shows how the wren and byteena signals control the RAM operations.
3–2:
and
XXXX
XX
an
FFFF
“Single-Clock Mode” on page
doutn
FFFF
®
II software. The setting can either be the newly written data or
10
a0
FFFF
ABFF
ABCD
01
a1
FFCD
11
a2
3–16.
ABCD
ABFF
a0
FFCD
Cyclone III Device Handbook, Volume 1
ABFF
“Single-Port Mode” on
(Note 1)
ABCD
a1
XXXX
XX
FFCD
a2
ABCD
3–5