EP3C120F484I7 Altera, EP3C120F484I7 Datasheet - Page 222

• Manufacturer Part Number: EP3C120F484I7
• Description: IC CYCLONE III FPGA 120K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F484I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 283
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 283
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–62
Table 9–19. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows
Cyclone III Device Handbook, Volume 1
FACTORY
ACTIVE_DISENGAGE
CONFIG_IO
JTAG Boundary Scan Instructions (no
JTAG_PROGRAM)
JTAG Instruction
I/O Reconfiguration
Use the CONFIG_IO instruction to reconfigure the I/O configuration shift register
(IOCSR) chain. This instruction allows you to perform board-level testing prior to
configuring the Cyclone III device family or waiting for a configuration device to
complete configuration. After the configuration is interrupted and JTAG testing is
complete, the part must be reconfigured using the PULSE_NCONFIG JTAG
instruction or by pulsing the nCONFIG pin low.
You can issue the CONFIG_IO instruction any time during user mode. The
CONFIG_IO instruction cannot be issued when nCONFIG pin is asserted low (during
power up) or immediately after issuing a JTAG instruction that triggers
reconfiguration. For more information about the wait-time for issuing the CONFIG_IO
instruction, refer to
When using CONFIG_IO instruction, you must meet the following timing restrictions:
■
■
■
Table 9–18. Wait Time for Issuing the CONFIG_IO Instruction
Use the ACTIVE_DISENGAGE instruction with CONFIG_IO instruction to interrupt
configuration.
CONFIG_IO usage scenarios.
Wait time after the nCONFIG pin is released
Wait time after PULSE_NCONFIG or ACTIVE_ENGAGE is
issued
CONFIG_IO instruction cannot be issued during the nCONFIG pin low
Observe 230 μs minimum wait time after any of the following conditions are met:
■
■
■
Wait 230 μs after power up with nCONFIG pin high before issuing the CONFIG_IO
instruction (or wait for the nSTATUS pin to go high)
nCONFIG pin goes high
Issuing the PULSE_NCONFIG instruction
Issuing the ACTIVE_ENGAGE instruction, before issuing the CONFIG_IO
instruction
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table 9–19
NA
PS
O
R
O
Table
Configuration Scheme and Current State of the Cyclone III Device Family
Prior to User Mode
Wait Time
Configuration)
(Interrupting
FPP
NA
O
R
O
9–18.
lists the sequence of instructions to use for various
NA
AS
O
R
O
AP
(4)
NA
O
R
O
PS
NA
O
R
O
(Note 1)
User Mode
FPP
NA
O
R
O
(Part 1 of 2)
NA
AS
© December 2009 Altera Corporation
O
R
O
NA
AP
(4)
O
O
R
230 ms
230 ms
Time
NA
PS
—
—
Configuration Features
R
Power Up
FPP AS
NA
—
—
R
—
NA NA
—
R
AP
(4)
NA
—
—