EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 120
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EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Configuration
3–6
Stratix II Device Handbook, Volume 1
The PLL_ENA pin and the configuration input pins
dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input
buffer. The VCCSEL input pin selects which input buffer is used. The 3.3-
V/2.5-V input buffer is powered by V
buffer is powered by V
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by V
A logic high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and
a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to
comply with the logic levels driven out of the configuration device or
MAX
If you need to support configuration input voltages of 3.3 V/2.5 V, you
should set the VCCSEL to a logic low; you can set the V
bank that contains the configuration inputs to any supported voltage. If
nSTATUS
used as an input)
nCONFIG
CONF_DONE
(when used as an
input)
DATA[7..0]
nCE
DCLK
as an input)
CS
nWS
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
Table 3–4. Pins Affected by the Voltage Level at VCCSEL
®
(when used
II/microprocessor.
Pin
(when
3.3/2.5-V input buffer is
selected. Input buffer is
powered by V
VCCSEL = LOW (connected
CCIO
CCINT
.
Table 3–4
to GND)
and must be hardwired to V
C C P D
.
shows the pins affected by VCCSEL.
CCPD,
while the 1.8-V/1.5-V input
1.8/1.5-V input buffer is
selected. Input buffer is
powered by V
bank.
VCCSEL = HIGH (connected
(Table
Altera Corporation
CCIO
to V
CCPD
3–4) have a
C C I O
CCPD
of the I/O
or ground.
)
of the I/O
May 2007