EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 176
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EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
5–40
Stratix II Device Handbook, Volume 1
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M E G A R C
M E G AW E R E S U
M E G AW E R E H
M E G A B E S U
M E G A B E H
M E G A D ATA A S U
M E G A D ATA A H
M E G A A D D R A S U
M E G A A D D R A H
M E G A D ATA B S U
M E G A D ATA B H
M E G A A D D R B S U
M E G A A D D R B H
M E G A D ATA C O 1
M E G A D ATA C O 2
M E G A C L K L
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Synchronous read cycle
time
Write or read enable
setup time before clock
Write or read enable
hold time after clock
Byte enable setup time
before clock
Byte enable hold time
after clock
A port data setup time
before clock
A port data hold time
after clock
A port address setup
time before clock
A port address hold time
after clock
B port setup time before
clock
B port hold time after
clock
B port address setup
time before clock
B port address hold time
after clock
Clock-to-output delay
when using output
registers
Clock-to-output delay
without output registers
Minimum clock low time 1,250
Parameter
1,866 2,774 1,866 2,911 1,777
1,950 2,899 1,950 3,042 1,857
Min
144
243
589
241
243
589
241
480
(4)
39
50
39
50
50
Grade
-3 Speed
Max
(2)
715
1,312
Min
151
255
618
253
255
618
253
480
(4)
40
52
40
52
52
Grade
-3 Speed
Max
(3)
749
1,866
1,950
1,437
1,437
Min
165
165
279
279
677
677
277
277
279
279
677
677
277
277
457
480
(5)
44
44
57
57
44
44
57
57
57
57
-4 Speed
Grade
Note (1)
3,189 1,777
3,332 1,950 3,884
Max
821
1,866
1,675
Altera Corporation
Min
192
325
789
322
325
789
322
480
(4)
52
67
52
67
67
-5 Speed
Grade
3,716
Max
957
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps