EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 134
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EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Hot Socketing Feature Implementation in Stratix II Devices
4–4
Stratix II Device Handbook, Volume 1
Figure 4–1. Hot Socketing Circuit Block Diagram for Stratix II Devices
The POR circuit monitors V
stated until the device is in user mode. The weak pull-up resistor (R) from
the I/O pin to V
3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V
before V
the I/O pins from driving out when the device is not in user mode. The
hot socket circuit prevents I/O pins from internally powering V
V
powered.
Figure 4–2
I/O buffers. This design ensures that the output buffers do not drive
when V
than V
insertion. There is no current path from signal I/O pins to V
or V
tolerant circuit capacitance.
CCINT
Resistor
Pull-Up
CCPD
Weak
PAD
, and V
CCIO
CCIO
CCIO
during hot insertion. The V
. This also applies for sudden voltage spikes during hot
shows a transistor level cross section of the Stratix II device
is powered before V
and/or V
CCPD
R
CCIO
when driven by external signals before the device is
Output
is present to keep the I/O pins from floating. The
CCINT
CCINT
and/or V
CCINT
voltage level and keeps I/O pins tri-
PAD
Input Buffer
to Logic Array
CCPD
Tolerance
or if the I/O pad voltage is higher
Voltage
Control
leakage current charges the 3.3-V
are powered, and it prevents
Output Enable
Altera Corporation
Hot Socket
Pre-Driver
Output
CCINT
Power On
Monitor
Reset
May 2007
CCIO
or V
,
CCIO