EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 57
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
May 2007
global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Figure 2–31. Global Clocking
Regional Clock Network
There are eight regional clock networks RCLK[7..0] in each quadrant of
the Stratix II device that are driven by the dedicated CLK[15..0] input
pins, by PLL outputs, or by internal logic. The regional clock networks
provide the lowest clock delay and skew for logic contained in a single
quadrant. The CLK clock pins symmetrically drive the RCLK networks in
a particular quadrant, as shown in
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Figure 2–31
Figure
Stratix II Device Handbook, Volume 1
CLK[15..12]
Global Clock [15..0]
2–32.
shows the 16 dedicated CLK
Stratix II Architecture
CLK[11..8]
2–49