EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 84
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EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure
Figure 2–51. Stratix II IOE in Bidirectional I/O Configuration
Notes to
(1)
(2)
2–76
Stratix II Device Handbook, Volume 1
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–51:
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
Figure 2–51
shows the IOE in bidirectional configuration.
Output Register
Input Register
OE Register
D
ENA
CLRN/PRN
ENA
D
CLRN/PRN
D
CLRN/PRN
ENA
Q
Q
Q
Drive Strength Control
Open-Drain Output
Pin Delay
Note (1)
Output
Input Register Delay
Logic Array Delay
Input Pin to
Input Pin to
OE Register
t
CO
Delay
V
CCIO
PCI Clamp (2)
V
Altera Corporation
CCIO
Bus-Hold
Circuit
Termination
On-Chip
Programmable
Pull-Up
Resistor
May 2007