EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 45
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–25. M-RAM Block LAB Row Interface
Note to
(1)
Altera Corporation
May 2007
Only R24 and C16 interconnects cross the M-RAM block boundaries.
Figure
LABs in Row
M-RAM Boundary
2–25:
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
LAB Interface
Blocks
L0
L1
L2
L3
L4
L5
Port A
Note (1)
M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Stratix II Device Handbook, Volume 1
Port B
R0
R1
R2
R3
R4
R5
LABs in Row
M-RAM Boundary
Stratix II Architecture
2–37