EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 130
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–38
Figure 5–28. Dynamic Phase Shifting Waveform
PLL Specifications
Arria II GX Device Handbook, Volume 1
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
f
f
The phasestep signal is latched on the negative edge of scanclk. In
this is shown by the second scanclk falling edge. phasestep must stay high for at
least two scanclk cycles. On the second scanclk rising edge after phasestep is
latched (the fourth scanclk rising edge in
and phasecounterselect are latched and the PLL starts dynamic phase-shifting
for the specified counters and in the indicated direction. On the fourth scanclk
rising edge, phasedone goes high to low and remains low until the PLL finishes
dynamic phase-shifting. You can perform another dynamic phase-shift after the
phasedone signal goes from low to high.
Depending on the VCO and scanclk frequencies, phasedone low time
(t
For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager
interface, refer to the
Megafunction User
For more information about PLL timing specifications, refer to the
Datasheet.
a
CONFIGPHASE
b
t
CONFIGPHASE
PHASEDONE goes low synchronous with SCANCLK
) may be greater than or less than one scanclk cycle.
Guide.
Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG)
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Figure
c
5–28), the values of phaseupdown
d
© July 2010 Altera Corporation
PLLs in Arria II GX Devices
Arria II GX Devices
Figure
5–28,
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