EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 135
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Overview
© July 2010 Altera Corporation
AIIGX51006-3.0
This chapter provides guidelines for using industry I/O standards in Arria
devices, including I/O features, standards and structure, banks, and design
considerations.
This chapter includes the following sections:
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■
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■
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This chapter contains feature definitions of Arria II GX I/O elements (IOEs). It
provides details about how an IOE works and its features. Arria II GX I/Os support a
wide range of features:
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■
■
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■
“Arria II GX I/O Standards Support” on page 6–2
“Arria II GX I/O Banks” on page 6–3
“Arria II GX I/O Structure” on page 6–5
“Arria II GX OCT Support” on page 6–11
“Arria II GX OCT Calibration” on page 6–14
“Arria II GX Termination Schemes for I/O Standards” on page 6–14
“Arria II GX Design Considerations” on page 6–21
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), reduced swing differential signal
(RSDS), mini-LVDS, bus LVDS (BLVDS), high-speed transceiver logic (HSTL), and
SSTL
Hard DPA block with serializer/deserializer (SERDES)
Programmable output current strength
Programmable slew rate
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination (R
On-chip differential termination (R
Programmable pre-emphasis
Programmable voltage output differential (V
6. I/O Features in Arria II GX Devices
S
OCT)
D
OCT)
OD
)
Arria II GX Device Handbook, Volume 1
®
II GX
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