EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 198
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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8–14
Figure 8–11. Receiver Datapath in Non-DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively.
(3) The rx_out port has a maximum data width of 10.
Arria II GX Device Handbook, Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
Figure
rx_out
8–11:
1
10
The Quartus
add to each trace. You can use the recommended trace delay numbers published
under the LVDS Transmitter/Receiver Package Skew Compensation panel and
manually compensate the skew on the PCB board trace to reduce the
channel-to-channel skews, thus meeting the timing budget between LVDS channels.
For more information about the LVDS Transmitter/Receiver Package Skew
Compensation report panel, refer to the “Arria II GX LVDS Package Skew
Compensation Report Panel“section in the
Megafunction User
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
®
II software Fitter Report panel reports the amount of delay you need to
IOE
Center/Corner PLL
Guide.
2
3
DOUT DIN
(Note
Multiplexer
Bit Slip
Clock
(LVDS_LOAD_EN,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
LVDS_diffioclk,
rx_outclk)
diffioclk
1), (2),
(3)
rx_inclock
SERDES Transmitter/Receiver (ALTLVDS)
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
N
3
(DPA_LO
DPA_diffioclk,
P P
rx_divfwdclk)
P P
© July 2010 Altera Corporation
AD_EN,
DPA Circuitr
DPA Cloc
Retimed
LVDS Clock Domain
P P
P P
Data
k
Differential Receiver
DIN
y
+
rx_in
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