EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 170
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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7–12
Figure 7–10. DQS Pins in Arria II GX I/O Banks for EP2AGX260 with the F1152 Package
Arria II GX Device Handbook, Volume 1
1
The corresponding DQ pins are marked as DQXY, where X indicates to which DQS
group the pins belong to and Y indicates whether the group is located on the top (T),
bottom (B), or right (R) side of the device. For example, DQS3B indicates a DQS pin
that is located on the bottom side of the device. The DQ pins belonging to that group
are shown as DQ3B in the pin table. See
The parity, DM, BWSn, and ECC pins are shown as DQ pins in the pin table.
The numbering scheme starts from the top-left side of the device going clockwise in a
die-top view.
view of the largest Arria II GX device.
PLL1
PLL4
DLL0
DQS1T
DQS24B
Figure 7–10
8B
3B
shows how the DQ/DQS groups are numbered in a die-top
8A
Arria II GX Device
3A
7A
4A
Figure 7–10
Chapter 7: External Memory Interfaces in Arria II GX Devices
7B
4B
DQS1B
DQS24T
for illustrations.
6B
6A
5B
5A
DLL1
Arria II GX Memory Interfaces Pin Support
PLL2
PLL5
PLL6
DQS1R
DQS24R
PLL3
© July 2010 Altera Corporation
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