EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 152
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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6–18
Figure 6–10. Arria II GX LVDS I/O Standard Termination
Note to
(1)
Arria II GX Device Handbook, Volume 1
R
p
= 170
Figure
LVDS_E_3R) (1)
External On-Board
(Single-Ended
OCT Receive
6–10:
LVDS Output
and R
with Three
OCT Receive
Network,
Termination
Resistor
(True LVDS
Termination
Output)
s
= 120
Figure 6–10
Differential LVPECL
Arria II GX devices support the LVPECL I/O standard on input clock pins only.
LVPECL output operation is not supported. LVDS input buffers are used to support
LVPECL input operation. AC-coupling is required when the LVPECL common mode
voltage of the output buffer is higher than Arria II GX LVPECL input common mode
voltage.
used at the receiver end are external to the device.
Figure 6–11. LVPECL AC-Coupled Termination
for LVDS_E_3R.
Figure 6–11
Output Buffer
Single-Ended Outputs
Differential Outputs
Differential Outputs
LVPECL
shows the details of LVDS termination in Arria II GX devices.
shows the AC-coupled termination scheme. The 50- resistors
0.1 μF
0.1 μF
External Resistor
Rs
Rs
(Note 1)
Rp
Z
Z
O
O
= 50 Ω
= 50 Ω
LVDS
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V
ICM
100 Ω
Arria II GX Termination Schemes for I/O Standards
Chapter 6: I/O Features in Arria II GX Devices
100 Ω
100 Ω
50 Ω
50 Ω
LVPECL Input Buffer
Arria II GX
Differential Inputs
Arria II GX OCT
Differential Inputs
Differential Inputs
© July 2010 Altera Corporation
Arria II GX OCT
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