EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 23
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Arria II GX Device Family Overview
Arria II GX Device Architecture
High-Speed LVDS I/O and DPA
Clock Management
Auto-Calibrating External Memory Interfaces
© July 2010 Altera Corporation
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Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to
1.25 Gbps
R
DPA circuitry and soft-CDR circuitry at the receiver automatically compensates for
channel-to-channel and channel-to-clock skew in source-synchronous interfaces
and allows for implementation of asynchronous serial interfaces with embedded
clocks at data rates from 150 Mbps to 1.25 Gbps
Emulated LVDS output buffers use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, BLVDS, and RSDS
standards.
Provides dedicated global clock networks (GCLKs), regional clock networks
(RCLKs), and periphery clock networks (PCLKs) that are organized into a
hierarchical structure that provides up to 148 unique clock domains
Up to six PLLs with seven outputs per PLL to provide robust clock management
and synthesis
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FPGA fabric can use the unused transceiver PLLs to provide more flexibility
I/O structure enhanced to provide flexible and cost-effective support for different
types of memory interfaces
Contains features such as OCT and DQ/DQS pin groupings to enable rapid and
robust implementation of different memory standards
An auto-calibrating megafunction is available in the Quartus II software for
DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM memory interface PHYs; the
megafunction takes advantage of the PLL dynamic reconfiguration feature to
calibrate based on the changes of process, voltage, and temperature (PVT).
D
OCT for high-speed LVDS interfacing
Independently programmable PLL outputs, creating a unique and
customizable clock frequency with no fixed relation to any other clock
Inherent jitter filtration and fine granularity control over multiply and divide
ratios
Supports spread-spectrum input clocking and counter cascading with PLL
input clock frequencies ranging from 5 to 500 MHz to support both low-cost
and high-end clock performance
Arria II GX Device Handbook, Volume 1
1–9
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